Systolic Carry-Save Modular Multiplication for Special Moduli
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing modular multiplication methods are inefficient for moduli of the form f·2e−1 and f·2e+1, particularly in hardware implementations, as they do not optimally utilize hardware or software resources, leading to higher complexity and critical path delays.
Innovation Solution
A systolic architecture using carry-save adder arithmetic with a combination of Full Adder and AND gate operations is employed, optimizing the processing elements for moduli of the form f·2e−1 and f·2e+1, reducing the number of gates and critical path delay by configuring the least significant elements with fewer Full Adders and AND gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a generic carry-save adder approach is used for modular multiplication, then the implementation can be performed, but the hardware resource utilization is not optimal and the critical path delay is increased
Solution Approach 1:
The patent applies local quality by differentiating the structure of processing elements based on their position in the systolic array. Least significant processing elements use a simplified structure with one Full Adder and one AND gate, while more significant elements use a full structure with two Full Adders and two AND gates. This localized optimization reduces overall hardware complexity while maintaining computational correctness for moduli of the form f·2^e±1.
Solution Approach 2:
The patent changes the computational parameters by exploiting the special form of the modulus (f·2^e±1) to simplify the Montgomery reduction algorithm. By recognizing that the modulus has a specific structure with a power of 2 component, the patent modifies the reduction steps to require fewer operations, thereby reducing the number of Full Adders and AND gates needed in each processing element.
2Speed
If standard Montgomery multiplication is implemented with full processing elements throughout, then computational correctness is ensured, but the critical path delay increases and processing speed decreases
Solution Approach 1:
The patent reduces critical path delay by applying local quality optimization to the least significant processing elements. These elements use a simplified structure with fewer logic gates (one Full Adder and one AND gate instead of two each), which directly reduces the propagation delay through these stages. The computational correctness is preserved because the special modulus form allows this simplification without losing any information needed for accurate reduction.
3Adaptability or versatility
If modular multiplication is performed with modulus not an exponent of 2, then general applicability is achieved, but the operation becomes expensive requiring additional work
Solution Approach 1:
The patent improves multiplication efficiency for specific moduli by changing the computational parameters to exploit the special form f·2^e±1. The Montgomery reduction algorithm is modified to take advantage of the power-of-2 component in the modulus, allowing certain terms to be simplified or eliminated. This parameter-specific optimization maintains versatility for this important class of moduli while significantly improving efficiency compared to generic approaches.
Data Source
AI summary
A computer processing system having at least one accelerator operably configured to compute modular multiplication with a modulus of special form and having a systolic carry-save architecture configured to implement Montgomery multiplication and reduction and having multiple processing element types composed of Full Adders and AND gates.