Systolic Dot Product Unit for Neural Network Throughput
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Solution Overview
Problem
Existing graphics processing units (GPUs) lack specialized hardware logic to efficiently accelerate dot product operations, which are crucial for machine-learning specific tasks, leading to suboptimal performance in executing neural network processing and related computations.
Innovation Solution
Incorporating special-purpose hardware logic within GPUs to enable direct access and acceleration of dot product operations, utilizing systolic dot product instructions and matrix multiplication units to enhance processing efficiency for neural network computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general-purpose graphics execution units are used for dot product operations, then the GPU can maintain versatility for various graphics tasks, but the throughput and efficiency of neural network processing deteriorates
Solution Approach 1:
The GPU architecture is segmented into general-purpose execution units for graphics tasks and specialized dot product units for neural network computations. This segmentation allows each component to be optimized for its specific function, with the dot product units providing accelerated throughput while the general-purpose units maintain graphics versatility.
Solution Approach 2:
A specialized dot product instruction acts as an intermediary between the general-purpose execution units and the underlying computation resources. This instruction enables efficient dot product operations by utilizing dedicated hardware paths, thereby improving neural network processing throughput without compromising the versatility of the general-purpose GPU architecture.
2Productivity
If specialized hardware logic is added to accelerate dot product operations, then neural network processing efficiency improves, but device complexity increases
Solution Approach 1:
The specialized dot product hardware logic is designed to perform multiple functions within the neural network processing pipeline, including dot product computation, accumulation, and result storage. This multi-functionality reduces the need for separate dedicated units for each operation, thereby limiting the increase in device complexity while maintaining high throughput.
Solution Approach 2:
The dot product computation logic is merged with the accumulation logic in a single unified hardware unit. This merging eliminates the need for separate computation and accumulation stages, reducing overall device complexity while achieving accelerated neural network processing throughput through the specialized hardware path.
Data Source
AI summary
Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch a single instruction for execution, a decode unit to decode the single instruction into a decoded instruction, wherein the decoded instruction is to cause the graphics processing unit to perform a set of parallel dot product operations on elements of input matrices, and a systolic dot product unit to execute the decoded instruction across one or more parallel processor lanes using multiple systolic layers associated with multiple pipeline stages. The multiple pipeline stages include one or more sets of interconnected multipliers and adders to compute multiple concurrent dot products.