Systolic Array Input Reduction for Arbitrary Bit-Length MAC
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Solution Overview
Problem
Traditional systolic arrays face challenges in supporting arbitrary bit-length inputs without significant increases in power consumption, size, and complexity, leading to inefficiencies in processing shorter bit-lengths and increased costs for supporting longer bit-lengths.
Innovation Solution
A systolic array with reducers that convert inputs to reduced bit-lengths, enabling single-pass or multiple-pass computations to maintain performance and efficiency, allowing arbitrary bit-length inputs while using lower-cost, lower-power elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the systolic array supports increased bit-lengths (e.g., 32-bit floating-point numbers), then computational accuracy is improved, but processing speed and power consumption are negatively impacted
Solution Approach 1:
The input data with increased bit-length is segmented into multiple reduced bit-length inputs that can be processed in parallel or sequentially by the systolic array elements, allowing accurate computation without requiring each element to natively support the full bit-length
Solution Approach 2:
The bit-length parameter of the input data is dynamically adjusted or reduced to match the native capabilities of the systolic array elements, optimizing processing speed while maintaining computational accuracy through multiple passes or reduced precision operations
2Measurement precision
If the systolic array supports increased bit-lengths, then computational accuracy is improved, but device size and complexity increase
Solution Approach 1:
The processing task is segmented into multiple stages where input data is broken down into reduced bit-length components, allowing the use of simpler processing elements that don't require complex circuitry to handle high bit-lengths directly
Solution Approach 2:
An intermediary data representation format is introduced where high bit-length inputs are converted into multiple reduced bit-length values that serve as intermediates, enabling accurate computation through simpler processing elements
3Measurement precision
If the systolic array supports increased bit-lengths, then computational accuracy is improved, but power consumption increases
Solution Approach 1:
The computation is segmented into multiple passes processing reduced bit-length data, reducing the power consumption of each individual processing element while achieving the same computational accuracy through accumulated results
Solution Approach 2:
Simpler, lower-power processing elements are used that can handle reduced bit-length data, replacing the need for expensive, high-power elements that would be required to natively support increased bit-lengths
Data Source
AI summary
Systems and methods are provided to perform multiply-accumulate operations of reduced precision numbers in a systolic array. Each row of the systolic array can receive reduced inputs from a respective reducer. The reducer can receive a particular input and generate multiple reduced inputs from the input. The reduced inputs can include reduced input data elements and/or a reduced weights. The systolic array may lack support for inputs with a first bit-length and the reducers may reduce the bit-length of a given input from the first bit-length to a second shorter bit-length and provide multiple reduced inputs with second shorter bit-length to the array. The systolic array may perform multiply-accumulate operations on each unique combination of the multiple reduced input data elements and the reduced weights to generate multiple partial outputs. The systolic array may sum the partial outputs to generate the output.