Systolic Array Matrix Multiplier With Local Data Retention
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Solution Overview
Problem
Existing systolic array matrix multipliers face performance degradation due to bus bandwidth limitations and inefficient use of processing elements, especially when handling matrices of varying sizes or parallel data input/output operations.
Innovation Solution
The systolic array matrix multiplier employs a configuration where data is relayed in a bucket brigade manner within processing elements, minimizing bus bandwidth requirements by retaining data within flip-flops and using multiplexers to manage data flow, allowing continuous matrix operations without re-inputting data during execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is re-input through bus during matrix multiplication operations, then processing can continue, but bus bandwidth requirements increase and performance degrades
Solution Approach 1:
The patent extracts the data storage function from the bus system and places it within the processing elements themselves. Each processing element contains flip-flops that retain matrix elements locally, eliminating the need for continuous bus access during multiplication operations. This extraction of the storage function resolves the contradiction by maintaining productivity while reducing bus bandwidth consumption to minimal levels.
Solution Approach 2:
Processing elements perform self-service by retaining necessary data internally and autonomously completing multiplication operations without requiring external data input during operation. The flip-flops within each processing element enable self-contained operation, allowing the system to maintain high throughput without burdening the bus system, thus resolving the bandwidth bottleneck.
2Device complexity
If processing elements are arranged in a fixed matrix configuration, then structure is simplified, but adaptability to different matrix sizes and operations is reduced
Solution Approach 1:
The patent implements universality by designing processing elements with multiple input and output terminals that can handle different data flow patterns. Each processing element can operate in multiple modes (e.g., different input/output configurations), allowing the same fixed matrix structure to adapt to various matrix sizes and operation types without changing the physical arrangement, thus resolving the contradiction between structural simplicity and operational versatility.
3Adaptability or versatility
If data flows through multiple paths in processing elements, then operational flexibility increases, but device complexity increases
Solution Approach 1:
The patent merges the data retention and data routing functions into a unified processing element structure. The flip-flops and selectors are integrated within each processing element rather than being separate components, allowing multiple data paths to be managed through a compact, unified design. This merging approach enables operational flexibility while controlling device complexity through functional integration.
Data Source
AI summary
A systolic array matrix multiplier executes matrix multiplication and includes processing element which each includes: a first holder that retains each element of a first matrix received from a first input terminal provided on one end side; a first path that outputs an output of the first holder to a first output terminal provided on another end side; a second holder that retains each element of the first matrix received from a second input terminal provided on the another end side; a second path that outputs an output of the second holder to a second output terminal provided on the one end side; a product-sum operator coupled to the first path; a first selector that couples the first path or the second input terminal to the second path; and a second selector that couples the second path or the output of the first holder to the first path.