Systolic Modular Polynomial Multiplier for Low-Latency Cryptography
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Solution Overview
Problem
Existing modular polynomial multiplication methods in cryptography face challenges with high latency and complexity, particularly in large-degree polynomial operations, which impact the efficiency of cryptographic processes.
Innovation Solution
A modular polynomial multiplier architecture is developed, utilizing a systolic structure with processing elements, delay units, and modular reduction techniques to achieve low latency and full hardware utilization, incorporating a fast-parallel modular polynomial multiplication approach that integrates modular reduction at the merging level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional modular polynomial multiplication methods are used, then the multiplication can be performed, but the latency is high and the processing speed is slow
Solution Approach 1:
The polynomial multiplication is divided into multiple parallel processing elements, each handling specific coefficient calculations. The processing elements are organized in a systolic array structure where multiplication and addition operations are segmented across multiple units working simultaneously, reducing overall computation latency.
Solution Approach 2:
The patent transforms the sequential polynomial multiplication into a two-dimensional systolic array architecture. Data flows through the array in both horizontal and vertical directions, allowing simultaneous multiplication and accumulation operations across multiple stages, effectively reducing the time complexity from O(n²) sequential operations to parallel processing.
2Loss of time
If a systolic structure with multiple processing elements is used, then latency is reduced, but the device complexity increases
Solution Approach 1:
Each processing element in the systolic array is designed as a universal unit capable of performing both multiplication and addition operations. The same hardware structure is reused across multiple stages, with data flowing through different stages performing different mathematical operations, reducing overall device complexity through functional reuse.
Solution Approach 2:
The systolic array maintains continuous data flow through all processing elements without idle stages. Each processing element continuously receives input data, performs computation, and passes results to the next stage, eliminating wasted computational cycles and reducing the need for complex control logic to manage idle periods.
3Productivity
If parallel processing is implemented, then processing speed improves, but hardware resource overhead increases
Solution Approach 1:
The patent merges multiplication and addition operations into unified processing elements where the output of one multiplication feeds directly into an addition unit within the same stage. This merging eliminates the need for separate multiplication and addition hardware blocks, reducing overall resource overhead while maintaining parallel processing throughput.
Data Source
AI summary
A modular polynomial multiplier includes a plurality of processing elements. Each includes a multiplication unit, an addition unit and a delay unit. The addition unit has an input connected to the output of the multiplication unit. The delay unit is connected to the output of the addition unit delays values by one clock cycle. The first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial and the second input of the multiplication unit of each processing element is connected to one of an input line carrying a sequence of coefficients of a second polynomial having n coefficients and a delay line carrying the sequence of coefficients of the second polynomial delayed by n clock cycles and negated.