Systolic PE Array Pipelining for GPU Resource Collision
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Solution Overview
Problem
Existing GPU architectures face performance degradation due to cache misses and resource collisions in SIMD-based shader processors, leading to inefficient usage of processing elements and increased storage needs for thread statuses.
Innovation Solution
A systolic data processing apparatus and method where a control unit pipelines instructions through a processing element array, allowing new instructions to be fetched and executed at each cycle, with resources shared efficiently and thread statuses not stored upon cache misses, enabling continuous operation and reduced idle time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If all processing elements access operation resources at the same time to execute special and texture instructions, then instruction execution is enabled, but resource collisions occur and performance decreases
Solution Approach 1:
The patent implements periodic action by enabling processing elements to access operation resources in alternating cycles rather than simultaneously. Special function units are accessed in one cycle while texture caches are accessed in another cycle, creating a periodic pattern that eliminates resource collisions while maintaining continuous instruction execution across different time periods
Solution Approach 2:
The patent applies dynamics by making the resource access pattern flexible and adaptive rather than static. The system dynamically switches between different access patterns based on instruction type and timing, allowing processing elements to access special function units or texture caches at different times according to operational needs, thereby optimizing resource utilization and preventing collisions
2Quantity of substance
If processing elements wait for cache operations to complete before fetching new threads, then storage space is reduced, but processing element usage is significantly lowered and overall performance decreases
Solution Approach 1:
The patent implements continuity of useful action by ensuring that while some processing elements are completing cache operations, other processing elements continuously fetch and execute new threads without waiting. This eliminates idle time and maintains continuous productive action across the processing element array, preventing performance degradation while managing storage space efficiently
Solution Approach 2:
The patent applies preliminary action by pre-fetching new threads into processing elements before previous cache operations complete. The control unit anticipates the need for new threads and prepares them in advance, allowing seamless transition between threads without waiting for cache operations to finish, thereby maintaining high processing element utilization
3Quantity of substance
If processing elements stop operations to wait for remaining threads to complete, then storage space is reduced, but partial processing element usage is significantly lowered
Solution Approach 1:
The patent implements periodic action by creating alternating phases where processing elements either execute threads or fetch new threads in a regular cycle. This periodic switching ensures that processing elements are rarely idle, as they continuously alternate between computation and thread loading tasks, maintaining high utilization while minimizing storage requirements for thread states
Data Source
AI summary
A systolic data processing apparatus includes a processing element (PE) array and control unit. The PE array comprises a plurality of PEs, each PE executing a thread with respect to different data according to an input instruction and pipelining the instruction at each cycle for executing a program. The control unit inputs a new instruction to a first PE of the PE array at each cycle.