Systolic Random Number Generator Using Ring Oscillator Array
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current random number generators lack efficient hardware-based solutions for generating high-quality random numbers, particularly in cryptographic applications, where they are essential for secure data transmission and other statistical analyses.
Innovation Solution
A systolic array configuration using cells with oscillators, flip-flops, and exclusive OR gates, combined with a physical unclonable function (PUF) from SRAM, provides a robust and high-speed random number generator, leveraging meta-stability and entropy sources to produce unpredictable outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a hardware-based random number generator is implemented, then generation speed and quality are improved, but device complexity increases
Solution Approach 1:
The system divides the random number generation function into multiple independent cells arranged in a systolic array. Each cell contains an oscillator, flip-flops, and logic gates that operate independently but contribute to the overall random number generation, distributing the complexity across modular units rather than a single complex device
Solution Approach 2:
The patent transitions from traditional single-dimensional or software-based RNG approaches to a two-dimensional systolic array architecture. This spatial arrangement allows parallel processing of random number generation across multiple cells, improving throughput while maintaining manageable complexity through structured organization
2Reliability
If multiple entropy sources are combined in the systolic array, then output quality and unpredictability are improved, but manufacturing precision requirements increase
Solution Approach 1:
The system varies parameters across different cells in the systolic array, including oscillator frequencies, feedback tap selections, and logic gate configurations. This parameter diversity ensures that each cell contributes unique entropy characteristics, improving overall randomness quality while allowing standard manufacturing tolerances through parametric variation rather than requiring ultra-precise fabrication
Solution Approach 2:
The patent combines multiple types of entropy-generating components (oscillators with different characteristics, flip-flops, logic gates) within each cell and across the array. This composite approach creates a heterogeneous system where diverse physical phenomena contribute to randomness, improving reliability while the modular cell design simplifies manufacturing by repeating standardized composite units
3Productivity
If a systolic array architecture is used, then generation speed is improved, but device area increases
Solution Approach 1:
The patent merges multiple functions into each systolic array cell, including oscillation generation, state storage via flip-flops, logical operations, and inter-cell communication. This functional integration allows parallel random number generation across multiple cells while minimizing the area per functional unit, achieving high throughput without linearly increasing total chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The systolic random number generator delivers high-quality, unpredictable outputs with limited single-point failure tolerance, suitable for cryptographic systems, and can be implemented in FPGAs or integrated circuits, addressing the need for reliable random number generation in secure data processing.
Implementation Method 1
leveraging meta-stability and entropy sources to produce unpredictable outputs
Data Source
AI summary
Systems and methods for a random number generator including a systolic array to provide a random number output. In one approach, the systolic array can be arranged in two or greater dimensions, and each cell of the array comprises a ring oscillator. Data is read from a random access memory to provide the inputs to the systolic array. A linear feedback shift register receives the random number output as a feedback signal used to address the memory to read data to provide as the inputs to the systolic array.