T-Coil Receiver Input Matching for High-Speed SERDES Links
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Solution Overview
Problem
High-speed data communication between cellular transceivers and modems requires numerous wires, which are difficult to manage and route due to space constraints, necessitating a more efficient method to achieve high-speed bidirectional communication.
Innovation Solution
A receiver and transceiver system utilizing a SERDES with T-coil circuits, termination impedance, and amplifiers, along with calibration and receive switches, to enable high-speed differential signaling with reduced pin count and improved input matching, allowing for calibration of offset voltage without affecting input impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a parallel connection is used between transceiver and modem, then data connection speed can reach about 2 Gbps per wire, but the number of wires required increases significantly (more than 16 wires in one direction for 32 Gbps connection)
Solution Approach 1:
The patent combines multiple parallel data channels into a single serial communication channel using SERDES technology. The transceiver and modem use a serial interface instead of multiple parallel wires, merging the function of many wires into one high-speed serial link that can achieve 32 Gbps or higher data rates.
Solution Approach 2:
The patent replaces the mechanical/physical parallel wire connection system with an electrical serial communication system using SERDES (Serializer/Deserializer) blocks. This substitution transforms the physical routing problem of multiple wires into an electrical signal processing problem that can be solved with fewer physical interconnects.
2Speed
If more than 32 wires are used for bidirectional communication, then 32 Gbps connection speed is achieved, but board design becomes difficult due to space constraints and routing complexity
Solution Approach 1:
The patent merges multiple high-speed serial lanes into a single bidirectional communication interface. Instead of requiring separate wires for each direction and each data channel, the SERDES implementation combines these functions into a unified serial link that reduces the physical footprint on the board while maintaining 32 Gbps or higher connection speeds.
Solution Approach 2:
The patent transitions from a spatial arrangement of multiple parallel wires (two-dimensional routing problem) to a temporal arrangement of serialized data bits (time-domain multiplexing). By encoding multiple data channels in the time domain rather than requiring simultaneous spatial separation, the board design complexity is significantly reduced.
3Measurement precision
If calibration switch is used to measure offset voltage of amplifier, then amplifier calibration is enabled, but input impedance matching may be affected
Solution Approach 1:
The patent performs amplifier offset voltage calibration during the manufacturing or initialization phase before the receiver enters normal operation. The calibration switch is temporarily activated to measure and compensate for offset voltages, and then deactivated. This preliminary calibration action ensures accurate offset compensation without affecting the input impedance matching during normal signal reception.
Solution Approach 2:
The patent extracts the calibration function from the normal signal path by using a calibration switch that temporarily connects the amplifier inputs during calibration mode. This separation allows offset measurement to be performed independently from the signal reception function, preventing interference with input impedance matching during normal operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system achieves high-speed bidirectional communication with reduced wire count, improved input matching, and minimized return loss, enabling efficient data transmission while maintaining a low pin count and preserving signal bandwidth.
Implementation Method 1
a first T-coil circuit (102; 302) at an input of the receiver (100; 300-1) and configured to receive an input signal
Implementation Method 2
a termination impedance (106; 306) coupled to the first T-coil circuit (102; 302) and configured to match an impedance of a transmission line (30)
Implementation Method 3
an amplifier (108) comprising a first input and a second input and configured to amplify a differential signal at the first and second inputs
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A receiver (100) includes a first T-coil circuit (102) at an input of the receiver (100) and configured to receive an input signal, a termination impedance (106) coupled to the first T-coil circuit (102) and configured to match an impedance of a transmission line (30) coupled to the first T-coil circuit (102), and an amplifier (108) including a first input and a second input and configured to amplify a differential signal at the first and second inputs, a calibration switch (110) coupled to the amplifier (108) and configured to selectively electrically connect or disconnect the first and second inputs of the amplifier (108), and a first receive switch (112) configured to selectively electrically connect or disconnect a center node (CNP) of the first T-coil circuit (102) and the amplifier (108).