T-coil IC Stacked Inductor Magnetic Coupling Bandwidth
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Solution Overview
Problem
As semiconductor IC device dimensions decrease and operating speeds increase, devices/transistors become vulnerable to electrostatic discharge (ESD), and existing T-coil circuit designs fail to effectively reduce high frequency signal loss due to ESD capacitance loading, which limits signal bandwidth.
Innovation Solution
A T-coil IC design featuring a first inductor core on a metal x layer and a second inductor core on a metal x-2 layer, connected by a via stack and a center tap on a metal x-1 layer, with specific turn configurations and thicknesses to optimize magnetic coupling coefficient and reduce ESD capacitance loading, thereby improving bandwidth extension.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional T-coil circuit designs are used, then ESD protection is provided, but high frequency signal loss due to ESD capacitance loading is not effectively reduced, limiting signal bandwidth
Solution Approach 1:
The patent transitions from planar inductor designs to three-dimensional stacked inductor cores on different metal layers (Mx and Mx-2). This vertical stacking creates magnetic coupling in the third dimension, enabling bandwidth extension while maintaining ESD protection functionality. The via stack connects the layered cores, establishing magnetic coupling coefficient k between layers to reduce high frequency signal loss.
Solution Approach 2:
The patent optimizes the magnetic coupling coefficient k between the stacked inductor cores as a key parameter. By controlling the coupling coefficient through the via stack design and core positioning, the system achieves reduced ESD capacitance loading effects and minimized high frequency signal loss, thereby extending signal bandwidth while maintaining ESD protection.
2Productivity
If device dimensions decrease and operating speed increases, then IC performance improves, but vulnerability to electrostatic discharge increases
Solution Approach 1:
The patent embeds multiple inductor cores within each other in a stacked configuration, with one core on the Mx layer and another on the Mx-2 layer. This nested three-dimensional structure provides enhanced ESD protection by distributing the protection function across multiple layers, while maintaining compact footprint suitable for scaled-down device dimensions and high operating speeds.
3Loss of energy
If magnetic coupling coefficient is optimized, then bandwidth is extended and high frequency signal loss is reduced, but device complexity increases
Solution Approach 1:
The patent divides the inductor structure into multiple discrete cores on separate metal layers, connected by via stacks. This segmentation allows independent optimization of each core and the coupling between them, enabling control of the magnetic coupling coefficient to reduce high frequency signal loss. The modular segmented structure manages complexity by breaking down the overall inductor into manageable discrete components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces high frequency signal loss and enhances bandwidth by optimizing the magnetic coupling coefficient, achieving improved ESD protection and circuit performance.
Implementation Method 1
A T-coil IC design featuring a first inductor core on a metal x layer and a second inductor core on a metal x-2 layer, connected by a via stack and a center tap on a metal x-1 layer, with specific turn configurations and thicknesses to optimize magnetic coupling coefficient
Data Source
AI summary
For a T-coil IC, a first inductor core is on an Mx layer and has n turns (n≥15/8). The first inductor core has a first-inductor-core-first end and a first-inductor-core-second end. A second inductor core is on an Mx-2 layer and has n turns. The second inductor core has a second-inductor-core-first end and a second-inductor-core-second end. The first-inductor-core-second end is connected to the second-inductor-core-first end by a via stack between the Mx and Mx-2 layers. A center tap is on an Mx-1 layer. The center tap is connected to the second inductor core at a node of the second inductor core. A first inductor is formed by the first inductor core between the first-inductor-core-first end and the first-inductor-core-second end and by the second inductor core between the second-inductor-core-first end and the node. A second inductor is formed by the second inductor core between the node and the second-inductor-core-second end.