T-Plug Isolation for 3D NAND Bit Line to SGD Short Prevention
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Solution Overview
Problem
During the manufacturing of 3D NAND flash memory devices, a potential defect arises from shorts formed during the contact formation between the bit line (BL) and the drain select gate (SGD), which can be challenging to prevent effectively.
Innovation Solution
A self-stop mechanism is implemented using a nitride/oxide film stack as an in situ etch mask over the SGD, preserving at least a portion of the oxide as a second mask layer, and forming a T-shaped polysilicon plug to protect the interface between the SGD and the conductive pillar, preventing shorts during BL-SGD contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation processes are used between BL and SGD, then manufacturing simplicity is maintained, but electrical shorts between BL and SGD occur
Solution Approach 1:
The patent applies preliminary action by forming the T-shaped polysilicon plug structure before completing the BL-SGD contact formation. The plug is created in a recess that extends through the SGD, and this protective structure is prepared in advance to prevent shorts during subsequent contact formation steps. The nitride/oxide film stack is also established beforehand as an etch mask to preserve the oxide layer that forms part of the protective barrier.
Solution Approach 2:
The T-shaped polysilicon plug acts as an intermediary protective element between the BL and SGD. This plug structure, combined with the preserved oxide isolation layer, serves as a mediator that physically separates and electrically isolates the BL from the SGD during contact formation, preventing direct electrical contact that would cause shorts while still allowing the contact to be formed.
2Reliability
If protective structures are added to prevent BL-SGD shorts, then electrical contact reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies self-service through the self-stop mechanism where the nitride/oxide film stack serves as an in-situ etch mask. During the etching process to form the recess, the differential etch rates between nitride and oxide layers automatically stop the etching when the oxide layer is exposed, without requiring external intervention or additional masking steps. The structure protects itself during the manufacturing process.
Solution Approach 2:
The protective structure combines multiple materials with different properties: the T-shaped polysilicon plug, the nitride isolation layer, and the oxide isolation layer. This composite structure leverages the different etch rates and material properties of each layer to create an effective short-prevention mechanism that integrates seamlessly into the existing manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively blocks shorts between the BL and SGD, ensuring reliable electrical contact and preventing defects in the memory device, thereby enhancing the manufacturing process and device integrity.
Implementation Method 1
forming a nitride isolation layer on the SGD layer, and forming an oxide isolation layer on the nitride isolation layer. The method also includes etching a pillar trench from the oxide isolation layer into the contact region of the semiconductor substrate
Implementation Method 2
forming a plug recess by etching sidewalls of the oxide isolation around the pillar trench to expose a portion of a top surface of the nitride isolation layer
Data Source
Figure 1
Figure 2
Figure 3a~3b
AI summary
A method of forming a memory structure (figures 3i - 3j), comprising: providing a layered semiconductor substrate (304) having a contact region (302), a source select gate (306, SGS) layer on the contact region, and a tiered stack of semiconductor layers (308) on the SGS layer; forming a drain select gate (312, SGD) layer on the tiered stack of the semiconductor substrate; forming a nitride isolation layer (314) on the SGD layer; forming an oxide isolation layer (316) on the nitride isolation layer; etching a pillar trench from the oxide isolation layer into the contact region of the semiconductor substrate; forming a central pillar (318, 320, 322) in the pillar trench from the contact region at least into the nitride isolation layer; forming a plug recess (328, 330) by etching sidewalls of the oxide isolation around the pillar trench to expose a portion of a top surface of the nitride isolation layer; forming a T-plug (332) in the plug recess; and forming an electrical contact (336) on the T-plug such that the T-plug (332) provides a barrier against electrical shorting from the electrical contact (336) to the SGD layer (312).