T-Shaped Buried Gate Electrode for DRAM Gate Control

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Solution Overview

Problem

As semiconductor devices shrink in size, the gate control ability for memory cells becomes a significant issue due to reduced sizes, affecting the performance and operation speed of dynamic random access memory (DRAM) devices.

Innovation Solution

The implementation of T-shaped buried gate electrodes in semiconductor devices, where the gate electrodes have portions extending across and into the source/drain regions, increasing the effective gate width and improving gate control ability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If semiconductor device size is reduced, then integration density increases, but gate control ability deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidgate control ability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The gate electrode is extended from a planar configuration into a three-dimensional T-shaped structure by adding a vertical component that protrudes into the source/drain region. This dimensional transition increases the effective gate width and control volume without expanding the device footprint, thereby maintaining high integration density while improving gate control ability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The gate electrode is divided into two functional segments: a horizontal portion that spans across the channel and a vertical portion that extends into the source/drain region. This segmentation allows each portion to perform specialized functions - the horizontal part provides standard gate control while the vertical part enhances control into the source/drain regions, collectively improving overall gate control without increasing device area.

Inventive Principle:
Principle #1Segmentation

2Reliability

If gate electrode is extended into source/drain region, then gate control ability improves, but device complexity increases

Engineering Contradiction:
Improvegate control abilityVSAvoidgate electrode structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate electrode structure is merged with the source/drain region by extending the gate material continuously from the channel into the source/drain region. This merging creates a unified T-shaped structure that improves gate control while avoiding the need for separate components or complex assembly steps, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The extended gate electrode serves multiple functions simultaneously: it provides standard gate control over the channel, enhances control into the source/drain regions, and maintains electrical continuity. This multi-functionality reduces the need for additional specialized structures, keeping the overall device complexity manageable despite the improved control capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11677008B2Method for preparing semiconductor device with T-shaped buried gate electrode
Publication Date: 2023.06.13 NAN YA TECH
  • US11677008B2 patent drawing
  • US11677008B2 patent drawing
  • US11677008B2 patent drawing

AI summary

The present disclosure provides a method for preparing a semiconductor device with a T-shaped buried gate electrode. The method includes forming an isolation structure in a semiconductor substrate to define an active region, and forming a doped region in the active region. The method also includes etching the semiconductor substrate to form a first trench and a second trench. The first trench has a first portion extending across the doped region and a second portion extending away from the first portion, and the second trench has a third portion extending across the doped region and a fourth portion extending away from the third portion. The method further includes forming a first gate electrode in the first trench and a second gate electrode in the second trench.