T-Shaped Connecting Pad for Semiconductor Package Power Transfer

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Solution Overview

Problem

The increasing length of interconnection lines between semiconductor chips and passive elements leads to deterioration of power transmission characteristics, and the mounting of passive elements increases the overall height of semiconductor packages, making them unsuitable for smaller electronic products and three-dimensional integrated circuits.

Innovation Solution

A semiconductor package design featuring a T-shaped connecting pad with a passivation film, a mold layer, and a wiring structure that includes an insulating layer and wiring pattern, allowing for reduced interconnection length and improved power transfer while maintaining package size, by positioning the element between posts within the mold layer and using a T-shaped connecting pad for solder ball attachment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If passive elements are mounted on the bottom surface of the package, then the interconnection line length increases, but the power transmission characteristics deteriorate

Engineering Contradiction:
Improvemounting of passive elementsVSAvoidpower transmission characteristics
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The connecting pad extends vertically through the mold layer to create a three-dimensional interconnection structure. The first portion is at the bottom surface for passive element mounting, while the second portion extends upward to reduce the horizontal distance to the semiconductor chip, effectively moving the connection path from a long planar route to a shorter vertical route.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If passive elements are mounted on the bottom surface of the package, then the interconnection line length increases, but the overall height of the package increases

Engineering Contradiction:
Improvemounting of passive elementsVSAvoidoverall height of package
Core Design Contradiction:
Ease of manufactureVSLength of stationary object

Solution Approach 1:

The connecting pad structure is nested within the mold layer, with the first portion at the bottom surface and the second portion extending upward through the mold layer to reach the wiring structure. This nested configuration allows passive elements to be mounted at the bottom while maintaining a compact overall height by utilizing the vertical space within the existing package structure.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Loss of energy

If the interconnection line length is reduced, then power transmission characteristics improve, but the package design becomes more complex

Engineering Contradiction:
Improvepower transmission characteristicsVSAvoidpackage design
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The T-shaped connecting pad serves multiple functions: it provides mounting surface for passive elements at the bottom, creates vertical interconnection through the mold layer, and connects to the wiring structure on the top. This multi-functional design achieves short interconnection length without requiring separate components or additional complex structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230068587A1Semiconductor package
Publication Date: 2023.03.02 SAMSUNG ELECTRONICS CO LTD
  • US20230068587A1 patent drawing
  • US20230068587A1 patent drawing
  • US20230068587A1 patent drawing

AI summary

A semiconductor package including a passivation film, a mold layer on the passivation film, a connecting pad having a T shape, the T shape including a first portion and a second portion on the first portion, the first portion penetrating the passivation film, the second portion penetrating a part of the mold layer, a solder ball on the first portion of the connecting pad, an element on the second portion of the connecting pad, a wiring structure on the mold layer, the wiring structure including an insulating layer and a wiring pattern inside the insulating layer, and a semiconductor chip on the wiring structure may be provided.