T-Shaped Erase Gate Layout for Self-Aligned Memory Cells
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Solution Overview
Problem
The alignment of components in semiconductor floating gate memory cells, such as source, drain, control gate, and floating gate, is challenging due to the need for different lithography and etching processes, leading to overlay shift and poor channel length control, especially as design rules tighten.
Innovation Solution
A semiconductor memory device design featuring a substrate with source and drain diffusion regions, floating gates, dielectric cap layers, an erase gate with a T-shaped profile, and a select gate formed in a self-aligned manner on the sidewall of the dielectric cap layer, along with a tunnel oxide layer and insulating layers, to improve alignment and manufacturing precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different lithography and etching processes are used to define select gate and control gate, then the gates can be formed with different patterns, but overlay shift occurs and channel length control deteriorates
Solution Approach 1:
The patent combines the formation of select gate and control gate into a single lithography and etching process step. By using a unified process to define both gates simultaneously, the invention eliminates overlay shift between the two gates while maintaining the ability to create different gate patterns through appropriate mask design and etch parameter control.
2Length of moving object
If design rule of integration decreases, then the smallest lithographic feature size is reduced, but alignment precision requirements become more critical
Solution Approach 1:
By merging the select gate and control gate formation into one process step, the invention reduces the number of alignment operations required. This is particularly beneficial for advanced nodes with smaller feature sizes, as it eliminates cumulative overlay errors that would otherwise accumulate with multiple lithography steps.
3Adaptability or versatility
If multiple lithography and etching processes are used, then complex gate structures can be formed, but manufacturing complexity increases and yield decreases
Solution Approach 1:
The invention merges multiple gate formation operations into a single lithography and etching cycle, reducing process complexity while maintaining the capability to form complex gate structures. This approach decreases manufacturing steps, reduces process variability, and improves overall yield without sacrificing structural complexity.
Data Source
AI summary
A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.