T-Shaped Gate Trench for Precise Meta-Gate Height Control
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Solution Overview
Problem
The semiconductor industry faces challenges in controlling and reducing the final meta-gate height (MGH) during the meta-gate etching-back process due to variations in etching processes across different meta-gate layers and spacing loading, which affects the fabrication of three-dimensional designs like fin FETs and gate-all-around FETs.
Innovation Solution
A manufacturing method involving the formation of fin structures with alternating semiconductor layers, followed by the creation of sacrificial gate structures and gate spacers, and subsequent etching processes to form T-shaped gate trenches, allowing precise control of gate electrode height and minimizing height variations, thereby improving the meta-gate etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional meta-gate etching-back process is used, then fabrication process is simple, but meta-gate height control precision deteriorates due to etching process variations
Solution Approach 1:
The patent applies preliminary action by forming sacrificial gate structures before the final gate structure. These sacrificial structures (including sacrificial meta-gate layers and sacrificial gate electrodes) are deposited and patterned in advance to define the eventual gate trench dimensions. This preliminary patterning establishes precise height and width controls that are maintained through subsequent selective etching processes, resolving the height control precision issue while managing fabrication complexity through structured sequencing.
Solution Approach 2:
The patent uses sacrificial gate structures as intermediary elements that mediate between the fabrication process and the final gate structure. These intermediaries (sacrificial meta-gate layers, sacrificial gate electrodes, and gate spacers) serve as temporary placeholders and etching masks that enable precise gate trench formation. After the gate trenches are formed and work function metal layers are deposited, the sacrificial structures are removed, having fulfilled their mediating role in achieving precise meta-gate height control.
2Reliability
If multiple meta-gate layers are used, then device performance is improved, but etching process variations increase
Solution Approach 1:
The patent segments the gate structure into multiple functional layers: sacrificial meta-gate layers, gate spacers, work function metal layers, and conductive fill layers. Each layer is deposited and patterned separately with specific materials and thicknesses tailored to its function. This segmentation allows each layer to be optimized independently, maintaining device performance while reducing etching variations through selective processing of each segment rather than treating all meta-gate layers uniformly.
Solution Approach 2:
The patent employs parameter changes by varying material compositions, thicknesses, and deposition conditions for different gate layers. The sacrificial meta-gate layers use specific materials with distinct etch selectivities, gate spacers have controlled thicknesses to define trench dimensions, and work function metal layers have optimized thicknesses for electrical performance. These parameter variations enable precise control over etching processes for each layer, reducing overall process variations while maintaining high device performance.
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The method includes the following steps. A fin structure extending along a first direction and having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed, the upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. A sacrificial gate structure extending along a second direction perpendicular to the first direction is formed over the upper fin structure. Gate spacers are formed on the sacrificial gate structure. A portion of the sacrificial gate structure is removed to expose the gate spacers. Portions of the exposed gate spacers are removed to form a first gate trench with a first dimension along the first direction. The rest of the sacrificial gate structure is removed to form a second gate trench with a second dimension along the first direction under the first gate trench, wherein the first dimension is greater than the second dimension. A gate dielectric and a first work function metal layer sequentially covering the first and second gate trenches are formed, wherein a first portion of the first work function metal layer merge in the second gate trench, and a second portion of the first work function metal layer is located on sidewalls of the first gate trench. The second portion of the first work function metal layer is removed to expose the gate dielectric located on sidewalls of the first gate trench while remaining the first portion of the first work function metal layer. A second work function metal layer is formed over the first portion of the first work function metal layer to fill the first gate trench.