T-Shaped Metal Gate Structure for Transistor Leakage Reduction
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to reduce current leakage and improve transistor performance as critical dimensions shrink, particularly due to difficulties in forming high-quality metal gate structures within increasingly small gate openings.
Innovation Solution
A method involving the formation of a T-shaped metal gate structure within a gate opening, where the dummy gate layer is partially removed and the spacer is thinned to increase the opening dimension, allowing for improved metal gate formation and electrical isolation by using a high-k gate dielectric layer and an etch blocking layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the critical dimension of the MOS transistor is reduced to improve integration density, then the transistor size decreases, but current leakage increases and manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The gate structure is segmented into multiple components: dummy gate layer, spacer layer, and metal gate structure. The dummy gate layer is first formed and then partially removed to create a gate opening, allowing the metal gate structure to be formed separately and precisely within the opening. This segmentation enables better control over the final gate dimensions and improves manufacturing precision at scaled dimensions.
Solution Approach 2:
The dummy gate layer and spacer layer are formed in advance before the metal gate structure. The spacer layer is formed on the side wall of the dummy gate layer to define the gate opening dimensions. This preliminary action establishes a template that guides the subsequent formation of the metal gate structure, ensuring precise dimensional control even as critical dimensions are reduced.
2Area of moving object
If the critical dimension is reduced to improve integration density, then device size decreases, but current leakage increases
Solution Approach 1:
The high-k gate dielectric material is introduced as an intermediary layer between the metal gate electrode and the semiconductor channel. This high-k material provides superior electrical isolation and reduces current leakage through the gate, enabling the device to maintain low leakage currents even as dimensions are reduced and electric fields become more intense.
3Area of moving object
If the gate opening size is reduced to improve integration density, then transistor density increases, but the difficulty of forming metal gate structure increases
Solution Approach 1:
The gate formation process is segmented into distinct steps: forming the dummy gate layer, forming the spacer layer on its side wall, removing part of the dummy gate layer to create the gate opening, and finally forming the metal gate structure within the opening. This segmentation transforms a single difficult step into multiple manageable steps, each with controllable parameters, thereby reducing the overall difficulty of manufacturing.
Solution Approach 2:
The spacer layer is formed in advance on the side wall of the dummy gate layer to define the gate opening dimensions before the metal gate structure is formed. This preliminary action creates a self-aligned mask that simplifies the subsequent etching and deposition steps, making the formation of the metal gate structure easier and more precise even in reduced-size devices.
4Object-generated harmful factors
If high-k gate dielectric material is used to reduce current leakage, then electrical isolation improves, but device complexity increases
Solution Approach 1:
The gate structure is divided into functionally distinct segments: the high-k gate dielectric layer for electrical isolation, the metal gate electrode for field control, and the spacer layer for dimensional definition. Each segment performs a specific function, allowing the complex requirements of low leakage and precise dimensional control to be met through specialized components rather than a monolithic structure.
Solution Approach 2:
The gate structure employs composite materials: a high-k gate dielectric material (such as hafnium oxide) combined with a metal gate electrode material. This composite structure leverages the superior electrical isolation properties of the high-k material and the excellent electrical conductivity and field control of the metal electrode, achieving both low current leakage and precise gate control despite increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the forming quality of the metal gate structure, reduces current leakage, and improves transistor performance by enlarging the process window for contact plug formation and electrical isolation.
Implementation Method 1
to prevent a Fermi-level pinning effect and a boron penetrating effect from occurring between a high-k gate dielectric material and a conventional gate electrode material
Implementation Method 2
a dielectric material (which is generally referred to as a high-k gate dielectric material) having a high dielectric constant
Implementation Method 3
improves transistor performance by enlarging the process window for contact plug formation and electrical isolation
Data Source
AI summary
A semiconductor structure and a method for forming the same, and a transistor are provided. In one form, a method includes: providing a base, where a dummy gate layer is formed on the base, a spacer is formed on a side wall of the dummy gate layer, an interlayer dielectric layer is formed on the base exposed from the dummy gate layer and the spacer, and the interlayer dielectric layer exposes a top of the dummy gate layer and a top of the spacer; removing a portion of a height of the dummy gate layer to form a remaining dummy gate layer, where the remaining dummy gate layer and the spacer enclose a trench; thinning a spacer exposed from the remaining dummy gate layer along a direction perpendicular to a side wall of the trench; after the thinning, removing the remaining dummy gate layer to form a gate opening within the interlayer dielectric layer; and forming a metal gate structure in the gate opening. Through the thinning, a gate opening whose side wall is provided with a remaining spacer is T-shaped. That is, a dimension of a top opening of the gate opening is increased, so that difficulty in forming the metal gate structure within the gate opening is reduced. That is, forming quality of the metal gate structure within the gate opening is helped to be improved, thereby improving performance of the transistor.