T-Shaped MOSFET Gate Structure for Lower RF Gate Resistance
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Solution Overview
Problem
Existing MOSFET devices face challenges in reducing gate resistance and parasitic capacitance, which degrade RF performance, particularly at high frequencies, despite efforts to scale gate lengths below lithographic capabilities.
Innovation Solution
The introduction of a multiple-conductive layer T-shaped gate structure, utilizing poly-SiGe and polysilicon layers with conformal or non-conformal insulating side-spacers, reduces gate resistance and parasitic capacitance, enabling improved RF performance by minimizing gate length below lithographic limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate length is scaled down to improve RF performance, then frequency operation is improved, but gate resistance increases and parasitic capacitance worsens
Solution Approach 1:
The gate structure is segmented into multiple conductive layers (first conductive layer and second conductive layer) with different lengths. The first conductive layer has a shorter length than the second conductive layer, creating a T-shaped configuration. This segmentation allows the gate to achieve effective length scaling for high-frequency operation while the extended second conductive layer maintains lower resistance by providing additional conduction path.
Solution Approach 2:
The gate structure transitions from a conventional single-layer planar configuration to a multi-layer T-shaped configuration. By adding the vertical dimension with multiple conductive layers stacked and extending at different lengths, the design achieves both short effective gate length for high frequency and extended total conductive path for reduced resistance, resolving the contradiction through dimensional expansion.
2Reliability
If conventional single-layer gate structure is used, then manufacturing is simpler, but gate resistance is higher and RF performance is degraded
Solution Approach 1:
The gate structure uses composite conductive layers comprising a first conductive layer and a second conductive layer with different properties. The first conductive layer provides the primary gate function with shorter length, while the second conductive layer extends beyond to reduce resistance. This composite structure combines the benefits of both layer configurations to achieve superior RF performance.
Solution Approach 2:
The first conductive layer is positioned within or alongside the second conductive layer, creating a nested T-shaped configuration. The shorter first conductive layer is embedded in the structure formed by the extended second conductive layer, allowing both layers to contribute to gate function while minimizing parasitic effects and maximizing conductivity.
3Object-affected harmful factors
If T-shaped gate structure with multiple conductive layers is implemented, then gate resistance decreases and RF performance improves, but manufacturing complexity increases
Solution Approach 1:
The first conductive layer is formed first, establishing the base gate structure. Subsequently, the second conductive layer is deposited and patterned to extend beyond the first layer, creating the T-shape. This sequential formation allows each layer to be processed independently with standard fabrication techniques, making the complex structure manufacturable through preliminary preparation and stepwise construction.
Data Source
AI summary
Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.