T-shaped Structure Patterning for Sub-20 nm Microelectronic Features
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Solution Overview
Problem
Current microelectronic manufacturing techniques face challenges in creating small features using ArF lithography, as they require multiple patterning steps and high-cost EUV tools, leading to technical difficulties and increased costs.
Innovation Solution
The method involves forming T-shaped structures on a substrate using an undercuttable layer and imaging layer, where the pattern is transferred into the undercuttable layer to create undercut-formed features, allowing for the use of existing ArF lithography techniques and reducing the need for expensive EUV tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If multiple patterning processes (lithography-etch-lithography-etch) are used to reduce feature size, then feature dimensions can be reduced, but overlay and alignment issues prevent fabrication of dense lines
Solution Approach 1:
The process segments the patterning into distinct lithography and etch steps, where each lithography step creates a pattern that is then transferred via etch to the underlying layer. This segmentation allows independent optimization of each step's precision requirements.
Solution Approach 2:
The invention moves from 2D planar patterning to 3D vertical structures by forming trenches and filling them with different materials. This dimensional transition allows dense line fabrication without requiring perfect overlay between multiple lithography steps, as the vertical etch process defines the final feature dimensions.
2Manufacturing precision
If CVD spacer process is used to eliminate second lithography step, then overlay issues are addressed, but numerous CVD and etch steps result in high cost and accumulation of process errors
Solution Approach 1:
The process merges the spacer formation and pattern transfer steps by using the etch process to directly transfer the lithography pattern into the underlying layer, eliminating the need for separate spacer deposition and removal steps.
Solution Approach 2:
The invention extracts and eliminates redundant CVD and etch steps from the traditional spacer process, keeping only the essential lithography-etch sequence needed for pattern transfer, thereby reducing process complexity and error accumulation.
3Device complexity
If photoresist pattern is directly used as template for conformal film, then initial CVD steps are eliminated, but CVD process at high temperature can damage the photoresist pattern
Solution Approach 1:
Instead of depositing conformal film on the photoresist template (which would require high-temperature CVD), the process inverts the sequence by using the photoresist to define the etch pattern, then transferring that pattern via etch to the underlying layer, avoiding thermal exposure of the photoresist.
Solution Approach 2:
The process replaces the thermal CVD deposition mechanism with a mechanical/chemical etch mechanism, where the photoresist pattern is transferred through selective etching rather than through high-temperature film deposition, thereby protecting the photoresist from thermal damage.
4Object-affected harmful factors
If spin-on process at low temperature is used, then photoresist damage is avoided, but two lithography steps are still required which maintain overlay issues
Solution Approach 1:
The process performs preliminary pattern definition in the first lithography step, then uses etch to transfer and permanently define the pattern in the underlying layer before any second lithography step is performed, eliminating overlay issues between lithography steps.
Solution Approach 2:
The etch process acts as an intermediary that transfers the lithography pattern into the underlying layer with high precision, serving as a bridge between the lithography step and the final feature formation, thereby eliminating the need for subsequent lithography alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of microelectronic structures with features smaller than 20 nm using existing ArF lithography, reducing costs and technical complexities associated with EUV technology.
Implementation Method 1
The imaging layer is patterned to yield a pattern. The pattern is transferred into the undercuttable layer
Implementation Method 2
The undercut areas are filled with a selectively etchable composition
Data Source
AI summary
Methods of forming microelectronic structure are provided. The methods comprise the formation of T-shaped structures using a controlled undercutting process, and the deposition of a selectively etchable composition into the undercut areas of the T-shaped structures. The T-shaped structures are subsequently removed to yield extremely small undercut-formed features that conform to the width and optionally the height of the undercut areas of the T-shaped structures. These methods can be combined with other conventional patterning methods to create structures having extremely small feature sizes regardless of the wavelength of light used for patterning.