T-Type Gate HEMT with Insulating Layers for Parasitic Reduction
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Solution Overview
Problem
High electron mobility transistors (HEMTs) face challenges in achieving stability, reducing parasitic capacitance and resistance, maintaining fine widths, increasing breakdown voltage, and improving cutoff frequency due to limitations in substrate growth and gate electrode fabrication, particularly with conventional photolithography methods.
Innovation Solution
The use of a T-type gate electrode with multiple insulating layers (silicon nitride or silicon oxide) between the substrate and the gate electrode, along with a field plate electrode, to enhance stability and reduce parasitic capacitance, while employing a method that avoids the need for double-layered or triple-layered photoresist layers in the electron beam lithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography method is used to form gate electrode, then fabrication process is simple, but resolution is insufficient for forming fine width gate electrode
Solution Approach 1:
The gate electrode structure is segmented into T-type configuration with distinct head portion and foot portion, where the foot portion has narrow width formed by electron beam lithography and the head portion has wider width formed by photolithography. This segmentation allows each portion to be optimized by appropriate fabrication method.
Solution Approach 2:
Different regions of the gate electrode are given different widths to serve different functions: the foot portion has narrow width for high resolution and low parasitic capacitance, while the head portion has wider width for current carrying capability. This local quality differentiation resolves the contradiction between fine width requirement and fabrication simplicity.
2Manufacturing precision
If double-layered or triple-layered photoresist layers are used in electron beam lithography, then fine width gate electrode can be formed, but fabrication complexity and time increase
Solution Approach 1:
The gate electrode formation process is segmented into two stages: first forming the narrow foot portion using electron beam lithography with single photoresist layer, then forming the wider head portion using photolithography. This segmentation eliminates the need for complex multi-layer photoresist structures while achieving the desired fine width precision.
Solution Approach 2:
The T-type gate structure acts as an intermediary form that bridges the gap between electron beam lithography capability (fine width) and photolithography simplicity (ease of manufacture). The foot portion utilizes the precision of electron beam method while the head portion benefits from the simplicity of photolithography.
3Ease of manufacture
If conventional gate electrode structure is used, then fabrication is simple, but parasitic capacitance and resistance are high
Solution Approach 1:
The gate electrode is segmented into T-type structure with separated head and foot portions, allowing optimization of electrical characteristics. The narrow foot portion reduces parasitic capacitance between gate and channel, while the wide head portion provides low resistance current path.
Solution Approach 2:
Different portions of the gate electrode are given different local qualities (widths) to address different electrical issues: narrow width at the foot portion for reduced parasitic capacitance, and wide width at the head portion for reduced resistance. This local differentiation eliminates harmful factors while maintaining fabrication feasibility.
4Ease of manufacture
If lattice mismatch is not considered, then material selection is simple, but electron mobility is low
Solution Approach 1:
The alloy composition parameter of AlGaN is optimized to balance lattice mismatch and electron mobility. By adjusting the Al content in AlGaN layer, the patent achieves both reasonable lattice matching and high electron mobility in the GaN channel, resolving the contradiction between material selection simplicity and electron mobility.
Data Source
AI summary
A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer.