3-Level T-Type Inverter Control for Switching Loss and Overload
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Solution Overview
Problem
Existing 3-level pulse-controlled inverters with T-type circuit topology face challenges in managing switching losses and overloading of semiconductor switches with lower current-carrying capacity, particularly when operating at higher current intensities.
Innovation Solution
A dual operating mode control strategy for the 3-level pulse-controlled inverter, where the current is alternately conducted through the third bridge branch for a delay period during mode transitions, reducing switching losses and preventing overload by using semiconductor switches with lower current-carrying capacity in the third bridge branch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the inverter is operated in second operating mode with lower current-carrying capacity switches, then switching losses are reduced, but the current-carrying capacity is insufficient for high current intensities
Solution Approach 1:
The patent applies dynamic operation mode switching based on current intensity thresholds. The control unit dynamically transitions between first and second operating modes: in the first mode (for currents above threshold), current flows alternately through first/third bridge branches and second/third bridge branches; in the second mode (for currents below threshold), current flows alternately through first/second bridge branches with a delay period through the third bridge branch. This dynamic adaptation allows the system to use lower current-carrying capacity switches in the third bridge branch while maintaining reliability across different operating conditions.
Solution Approach 2:
The patent changes operational parameters (current threshold, operating mode, conduction path) based on the current intensity level. By monitoring current intensity and comparing it to a predefined threshold, the system adjusts which bridge branches conduct current and for how long. This parameter change enables the third bridge branch with lower current-carrying capacity switches to operate safely below the threshold while still contributing to reducing overall switching losses through the delayed conduction strategy.
2Loss of energy
If the current is conducted through the third bridge branch for a delay period, then switching losses are reduced by half, but the control complexity increases
Solution Approach 1:
The patent implements periodic action through the delay period mechanism. In the second operating mode, after current flows alternately through the first and second bridge branches, it is conducted through the third bridge branch for a specific delay period before switching to the next cycle. This periodic delayed conduction through the third bridge branch creates a structured switching pattern that reduces switching losses by half compared to continuous conduction, while the periodic nature makes the control logic manageable through clear temporal phases.
3Ease of manufacture
If semiconductor switches with lower current-carrying capacity are used in the third bridge branch, then cost is reduced, but they are prone to overloading at high current intensities
Solution Approach 1:
The patent employs feedback control through the control unit that continuously monitors current intensity and compares it against a predefined threshold value. Based on this feedback, the control unit determines which operating mode to activate. When current intensity exceeds the threshold, the system switches to the first operating mode that protects the lower current-carrying capacity switches in the third bridge branch from overload. This feedback mechanism enables the use of cost-effective lower-specification switches while maintaining reliability through intelligent operational control.
Data Source
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AI summary
The invention relates to a method for controlling a 3-level T-type pulse-controlled inverter (1). In a first operating mode of the pulse-controlled inverter (1), a current (I) is alternately conducted through a first bridge branch (B1) and a third bridge branch (B3) of the pulse-controlled inverter (1) during a first half-period of an alternating current to be generated by the pulse-controlled inverter (1), and alternately through a second bridge branch (B2) and the third bridge branch (B3) of the pulse-controlled inverter (1) during the second half-period. In a second operating mode of the pulse-controlled inverter (1), the current (I) is alternately conducted through the first bridge branch (B1) and the second bridge branch (B2), wherein upon each switching of the current conduction between the first bridge branch (B1) and the second bridge branch (B2), the current (I) is conducted through the third bridge branch (B3) for a delay period (Δt).The pulse inverter (1) is operated in the first operating mode when the current magnitude is less than a current threshold, and otherwise the pulse inverter (1) is operated in the second operating mode.