Two Transistor One Capacitor Memory Cell Vertical Interconnect Elimination
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Solution Overview
Problem
The integration of vertically stacked memory cells into integrated circuit architectures poses structural challenges, including electrical leakage and noise issues due to the need for vertical connections between the top and bottom of the memory cell, which can degrade the stored state and require complex circuitry.
Innovation Solution
The proposed solution eliminates the need for vertical lines by using a reference voltage applied to an upper digit line during a read operation, allowing the memory cell to be accessed without vertical connections, thereby reducing electrical leakage and noise, and enabling faster write and refresh times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If vertical connections are used to access vertically stacked memory cells, then memory integration is achieved, but electrical leakage and noise issues occur
Solution Approach 1:
The patent transitions from vertical connections (3D spatial approach) to a time-dimensional approach by applying reference voltages at specific timing moments. Instead of physically connecting through vertical lines, the system uses temporal sequencing of voltage applications to achieve memory cell access without harmful vertical interconnections.
Solution Approach 2:
The patent introduces reference voltages as intermediary signals that mediate between the control logic and the memory cell state. These reference voltages applied to digit lines serve as intermediaries that enable state determination without requiring direct vertical electrical connections that cause leakage and noise.
2Volume of moving object
If vertical connections are used for memory cell access, then stacked architecture is enabled, but complex circuitry is required
Solution Approach 1:
The patent extracts and removes the problematic vertical connection elements from the memory cell access circuitry. By eliminating the need for vertical interconnect lines between stacked cells, the design simplifies the overall circuit architecture while maintaining the benefits of vertical stacking through alternative voltage application methods.
3Measurement precision
If conventional read operations are used, then data can be sensed, but electrical interference degrades reliability
Solution Approach 1:
The patent establishes equipotential conditions by applying reference voltages to digit lines during read operations. This creates stable voltage potentials that eliminate electrical interference and noise, enabling reliable data sensing without degrading the stored state through electrical disturbances.
Data Source
AI summary
Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.