TaB Adhesion Layer in Metal Interconnects for Low Resistance
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Solution Overview
Problem
As semiconductor devices minimize, the pattern width of metal wiring and gaps between metal wiring decrease, leading to increased resistivity and resistive-capacitive (RC) delay due to electron scattering, and subsequent processes like air gap introduction or annealing cause metal wiring deterioration or breakage.
Innovation Solution
A semiconductor device with a metal interconnection structure that includes an adhesion layer of tantalum boride (TaB) or its alloy, combined with an interconnection layer of materials like Ru, Rh, Ir, Mo, Cu, Co, W, RuAl, NiAl, NbB2, MoB2, CuAl, CuAl2, and MoW, to reduce resistance and prevent metal wiring deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the pattern width of metal wiring is decreased to minimize semiconductor devices, then the integration density is improved, but the resistivity increases due to electron scattering
Solution Approach 1:
The patent uses composite material structures including adhesion layers (tantalum, tungsten, titanium, or their nitrides/oxides), barrier layers (ruthenium, rhodium, iridium, or their alloys), and copper interconnection layers. This multi-layer composite structure allows the metal wiring to maintain low resistivity even at reduced pattern widths by preventing electron scattering at interfaces and providing structural support
Solution Approach 2:
The patent changes material parameters by selecting specific materials with appropriate properties for each layer. The adhesion layers use materials with high binding energy to prevent delamination, barrier layers use materials with low diffusion coefficients to prevent copper migration, and the copper interconnection layer provides inherently low resistivity. These parameter optimizations enable reliable operation at smaller dimensions
2Area of moving object
If the gap between metal wiring is decreased to minimize semiconductor devices, then the integration density is improved, but the resistive-capacitive (RC) delay increases
Solution Approach 1:
The patent changes the dielectric parameter by using low-k dielectric materials with dielectric constants below 3.5, and in some embodiments between 2.0 and 3.0. This reduction in dielectric constant directly reduces the capacitive coupling between adjacent metal wiring, thereby reducing RC delay even when the gap between wires is minimized for higher integration density
3Reliability
If subsequent processes like air gap introduction or annealing are performed to solve resistivity increase, then the resistivity problem is addressed, but metal wiring deterioration or breakage occurs
Solution Approach 1:
The patent performs preliminary actions by forming robust adhesion layers and barrier layers before subsequent processing steps. The adhesion layers (tantalum, tungsten, titanium, or their nitrides/oxides) are deposited first to create strong bonding interfaces, and barrier layers are formed to protect the copper from oxidation and diffusion. This preliminary protection prevents metal wiring deterioration and breakage during air gap introduction, annealing, and other subsequent processes
Solution Approach 2:
The patent provides beforehand cushioning by creating multi-layer protective structures that absorb and distribute mechanical and thermal stresses. The adhesion layers and barrier layers act as cushioning layers that prevent stress concentration in the thin copper interconnection layer, thereby preventing breakage during subsequent processing operations such as annealing and air gap formation
Data Source
AI summary
Provided is a semiconductor device including an activation pattern extended in a first direction, a gate electrode having portions of the gate electrode spaced apart in the first direction on the activation pattern, and extending in a second direction intersecting the first direction, a gate contact on the gate electrode, a source/drain pattern on the activation pattern, a source/drain contact on the source/drain pattern, an insulation layer over the gate contact and the source/drain contact, a via penetrating the insulation layer, wherein the via is on at least one of the gate contact or the source/drain contact, an adhesion layer on the insulation layer, wherein the adhesion layer exposes an upper surface of the via, and an interconnection layer on the first adhesion layer, wherein the upper surface of the via is in contact with a first portion of the interconnection layer, and wherein the first adhesion layer includes tantalum boride (TaB) or an alloy of TaB.