TAB Tape Test Pad Overlap for Semiconductor Package Miniaturization
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Solution Overview
Problem
Conventional TAB tape carrier packages require rotating semiconductor chips by 180° for mounting, necessitating complex equipment modifications and increased test pad areas, leading to higher costs and inefficiencies in bonding accuracy and inspection processes.
Innovation Solution
A TAB tape design with overlapping input and output test pad areas allows for miniaturization without chip orientation changes, using a mask pattern to form adjacent pattern areas with integrated input and output test pads, reducing the overall test pad area and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semiconductor chips are rotated by 180° for mounting on TAB tape, then bonding accuracy can be improved, but equipment complexity increases and test pad area expands
Solution Approach 1:
The patent merges the input test pad area of one pattern area with the output test pad area of the adjacent pattern area by positioning them in overlapping regions. This allows shared use of test pad spaces between adjacent semiconductor packages, reducing the total test pad area without compromising bonding accuracy or requiring equipment modifications for chip rotation.
2Manufacturing precision
If semiconductor chips are rotated by 180° for mounting on TAB tape, then bonding accuracy can be improved, but the number of equipment modifications and inspection process complexity increases
Solution Approach 1:
The patent combines the inspection processes for adjacent pattern areas by positioning input test pads in overlapping regions where they can be inspected together with output test pads of neighboring packages. This eliminates the need for separate inspection procedures for rotated chips, simplifying the manufacturing process while maintaining bonding precision.
3Reliability
If separate input and output test pad areas are provided for each pattern area, then inspection coverage is improved, but test pad area and package size increase
Solution Approach 1:
The patent merges the input test pad area of one pattern area with the output test pad area of the adjacent pattern area by positioning them in overlapping regions. This allows shared use of test pad spaces between adjacent semiconductor packages, reducing the total test pad area while maintaining complete inspection coverage for all chips.
Solution Approach 2:
The overlapping test pad areas serve dual functions: they act as output test pads for one pattern area and input test pads for the adjacent pattern area. This multi-functional design reduces redundancy and minimizes the overall test pad area required for complete inspection coverage.
4Measurement precision
If test pads are aligned in multiple lines to accommodate fine pitch, then inspection capability is maintained, but package area and cost increase
Solution Approach 1:
The patent merges test pad arrangements from adjacent pattern areas into overlapping regions, allowing fine-pitch inspection capability to be achieved without expanding the overall package area. The shared test pad areas enable multi-line alignment for fine pitch while reducing total space requirements through spatial efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design minimizes the test pad area, reduces equipment complexity, and maintains bonding accuracy while allowing for efficient semiconductor package miniaturization without altering the chip orientation, thereby lowering production costs and improving inspection efficiency.
Implementation Method 1
using a mask including a mask pattern, wherein the mask pattern is for forming: a plurality of output test pads for use in inspection of a semiconductor chip; output terminal wires for connecting corresponding output terminals of the semiconductor chip to the output test pads; one or a plurality of input test pads placed in the overlapping area, for use in inspection of a semiconductor chip in the adjacent pattern area
Data Source
AI summary
Input test pads of an adjacent pattern area are placed in a vacant area of a layout area of output test pads, optimizing the layout area of test pads for use in inspection of a semiconductor chip. Thus, it is possible to miniaturize a semiconductor package.