Table-Driven Test-Port Architecture for Automated RTL Code Generation
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Solution Overview
Problem
The development and implementation of custom or proprietary test-port interfaces for ASICs are costly and resource-intensive, often requiring manual coding in RTL languages like Verilog or VHDL, which is complex and prone to logic bugs, especially in high-reliability applications where test-port usage requirements are stringent.
Innovation Solution
A new table-driven test-port architecture that allows for automated generation of RTL code for test-port interfaces using a test-port table specification, enabling the creation of address-detect and test-enable logic, one-hot multiplexer logic, and test-mode blocks to efficiently manage bidirectional test-port pins, facilitating scalable and reusable test-port implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual RTL coding is used for custom test-port interfaces, then flexibility and customization are improved, but development cost, time, and complexity increase
Solution Approach 1:
The patent uses template-based RTL code generation where pre-defined test-port interface templates are automatically instantiated and customized through configuration parameters. This copying approach allows flexible customization without manual coding, reducing development complexity while maintaining adaptability.
Solution Approach 2:
The invention creates a universal test-port interface framework that can handle multiple test modes and configurations through a single standardized architecture. This multi-functional design allows the same base code to serve different customization needs, reducing development effort while maintaining versatility.
2Adaptability or versatility
If manual RTL coding is used for custom test-port interfaces, then flexibility and customization are improved, but logic bugs and reliability issues increase
Solution Approach 1:
By copying from verified, pre-tested RTL code templates rather than writing custom code, the system inherits the reliability and correctness of the template code. This approach minimizes logic bugs while still allowing customization through parameter configuration.
Solution Approach 2:
The automated code generation system includes validation and verification mechanisms that check the generated RTL code for correctness and consistency. This feedback loop ensures that customized test-port interfaces maintain high reliability even with extensive customization.
3Adaptability or versatility
If manual RTL coding is used for custom test-port interfaces, then specific test-port requirements are met, but resource consumption and development effort increase
Solution Approach 1:
The system automatically generates RTL code by copying and instantiating pre-defined templates, eliminating the need for manual coding. This dramatically improves development efficiency while maintaining the ability to meet specific test-port requirements through configuration parameters.
Solution Approach 2:
The test-port interface templates are prepared in advance with all necessary logic and structure. This preliminary action allows rapid customization and deployment without time-consuming manual coding, significantly improving productivity while meeting specific requirements.
4Reliability
If proprietary test-port interfaces are implemented in custom ASICs, then high-reliability application requirements are met, but implementation cost and complexity increase
Solution Approach 1:
The automated RTL code generation system copies from proven, high-reliability template code, ensuring that the generated test-port interfaces meet high-reliability requirements. This approach makes implementation easier by eliminating manual coding errors and reducing verification effort.
Solution Approach 2:
The system achieves different test-port configurations and high-reliability performance by changing parameters in the generated code rather than manually redesigning the interface. This parameter-based customization simplifies implementation while maintaining high-reliability performance for different applications.
Data Source
AI summary
A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. The computer then completes the generation of the RTL code.