Translation Address Cache SMM Entry Segmentation
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Solution Overview
Problem
Conventional processors flush most cached address translations when entering or exiting system management mode (SMM), leading to improper operation and system failure due to false hits, and result in the loss of valuable translations that require time-consuming tablewalks upon resumption.
Innovation Solution
A processor with a translation address cache that includes a system management mode identifier for each entry, allowing only matching mode translations to be stored and flushed, thereby avoiding unnecessary invalidation of non-SMM entries during SMM transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all cached address translations are flushed when entering/exiting SMM, then system reliability is improved by avoiding false hits, but processor performance deteriorates due to loss of valuable translations requiring time-consuming tablewalks
Solution Approach 1:
The translation address cache is segmented into SMM entries and non-SMM entries using mode identifiers. This segmentation allows selective flushing of only SMM entries while preserving non-SMM entries, resolving the contradiction between reliability (avoiding false hits) and performance (retaining valuable translations).
Solution Approach 2:
Different parts of the cache are given different qualities based on their mode identifier tags. SMM entries are marked with a specific mode identifier that distinguishes them from non-SMM entries, enabling targeted flushing operations that maintain reliability while preserving performance-critical non-SMM translations.
2Reliability
If all cached address translations are flushed during SMM transitions, then system safety is improved by preventing improper operation, but loss of time increases due to required tablewalks upon resumption
Solution Approach 1:
The cache is segmented by mode identifiers, allowing the system to flush only SMM-specific entries while preserving non-SMM entries. This eliminates false hits during SMM transitions (improving safety) while avoiding unnecessary flushing of non-SMM translations (reducing time loss).
Solution Approach 2:
The mode identifier is preliminarily set before SMM entry, enabling the flush logic to selectively identify and flush only SMM entries. This preliminary differentiation prevents unnecessary flushing of non-SMM translations, reducing the time penalty associated with SMM transitions.
3Manufacturing precision
If mode identifiers are added to cache entries, then cache management precision is improved by enabling selective flushing, but device complexity increases due to additional cache structure
Solution Approach 1:
A mode identifier parameter is added to each cache entry to enable differentiation between SMM and non-SMM translations. This single parameter change provides the precision needed for selective flushing while minimizing the increase in overall cache structure complexity.
Data Source
AI summary
A processor including a memory that stores a system management mode (SMM) value indicative of whether the processor is in SMM, a translation address cache (TAC) that includes multiple entries for storing address translations, in which each entry includes an SMM identifier, hit logic that compares a lookup address with address translations stored in the TAC for determining a hit, in which the hit logic determines a hit only when a corresponding SMM identifier of an entry matches the SMM value, and entry logic that selects an entry of the TAC for storing a determined address translation and that programs an SMM identifier of the selected entry of the TAC to match the SMM value. The processor may include flush logic that distinguishes SMM entries, and processing logic that commands flushing upon entering and/or exiting SMM. Non-SMM entries may remain in the TAC when entering and exiting SMM.