TAD A/D Converter Delay Units Using Local Quality
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Solution Overview
Problem
TAD A/D converters face challenges in maintaining stable characteristics and low differential non-linearity due to manufacturing defects and dust particles, especially as transistor sizes decrease, leading to variations in delay units and inaccurate A/D conversion data.
Innovation Solution
The A/D converter design includes a pulse delay circuit with larger transistors to ensure uniform delay and reduce the impact of manufacturing defects, along with buffer circuits to match signal transmission delays, and a sampling clock signal generating circuit to increase resolution by adjusting phase differences, all implemented using CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor sizes are decreased to achieve miniaturization, then device integration density increases, but manufacturing precision deteriorates due to defects and dust particles
Solution Approach 1:
The patent applies local quality by making delay units with larger transistor sizes in critical regions where uniform delay is essential, while other parts of the circuit can use smaller transistors for miniaturization. This localized approach ensures that the most sensitive components (delay units) have the manufacturing precision needed to maintain uniform delay characteristics, while the overall device still achieves high integration density through smaller transistors in non-critical areas.
2Area of moving object
If transistor sizes are decreased for miniaturization, then device compactness improves, but reliability deteriorates due to increased sensitivity to manufacturing defects
Solution Approach 1:
The patent implements local quality by using larger transistor sizes specifically in delay units where reliability is critical for stable A/D conversion, while allowing smaller transistors in other circuit blocks. This selective sizing ensures that the most reliability-sensitive components are protected against manufacturing defects, maintaining conversion stability even as the overall device size is reduced through miniaturization in non-critical areas.
3Measurement precision
If uniform delay characteristics are enforced in delay units, then measurement precision improves, but device complexity increases due to additional buffer circuits
Solution Approach 1:
The patent applies segmentation by dividing the circuit into distinct functional blocks: delay units with larger transistors for uniform delay, and buffer circuits with smaller transistors for signal transmission. This segmentation allows each block to be optimized for its specific function - delay units prioritize uniformity and precision, while buffers handle signal conditioning - thereby achieving high measurement precision without requiring the entire circuit to be complex.
Solution Approach 2:
The patent uses local quality by applying different transistor sizing strategies to different circuit components. Delay units use larger transistors to ensure uniform delay characteristics and high measurement precision, while buffer circuits use smaller transistors to minimize their impact on overall delay and reduce complexity. This localized differentiation allows the system to achieve high precision where needed without unnecessarily increasing overall device complexity.
Data Source
AI summary
A TAD (time analog/digital) type of A/D converter has plural series-connected delay units each producing a delay in accordance with the level of a converter input voltage, with a first-stage delay unit receiving a pulse signal at commencement of each A/D conversion sampling interval, and a latch/encoder circuit detecting the total number of delay units traversed by the pulse signal by the end of the sampling interval, to obtain a numeric value expressing the input voltage level. To ensure uniformity of the delays of the delay units, these are formed using transistors of larger size than transistors of other circuits such as the latch/encoder circuit.