TAF-DPS Clock Distribution for Chip Skew Reduction
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Solution Overview
Problem
Modern integrated circuit designs face challenges in distributing a global clock signal due to increasing chip complexity, higher operating frequencies, and larger chip sizes, leading to significant skew, power consumption, and resource requirements in conventional tree and grid structures, as well as stability issues with distributed PLL arrays.
Innovation Solution
The implementation of a Time-Average-Frequency Direct Period Synthesizer (TAF-DPS) system that uses a low frequency global clock signal to generate functional clock signals locally in each area, reducing skew, noise, and power consumption, while providing frequency and phase synthesis capabilities to accommodate delay variations and data communication scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional tree or grid structures are used to distribute global clock signal, then the clock signal can be delivered to all clock sinks, but significant skew and jitter accumulate along the distribution paths
Solution Approach 1:
The chip is divided into multiple synchronous clock areas (SCAs), each with its own TAF-DPS clock source. This segmentation allows each area to generate its own clock signal locally, eliminating the accumulation of skew and jitter that occurs in centralized tree or grid distribution networks.
Solution Approach 2:
The TAF-DPS (Time-Average-Frequency Direct Period Synthesizer) pre-calculates and adjusts the clock signal parameters before distribution. By using time-average-frequency synthesis, the system compensates for distribution delays in advance, ensuring that clock signals arrive at all sinks with minimal skew.
2Speed
If high operating frequencies are used to improve chip performance, then processing speed increases, but clock skew and jitter become more significant
Solution Approach 1:
By dividing the chip into multiple SCAs with independent TAF-DPS sources, each operating at high frequency, the system achieves high overall performance while limiting the physical distribution distance for each clock signal, thereby reducing skew accumulation.
Solution Approach 2:
The TAF-DPS dynamically adjusts clock signal parameters including frequency and phase based on local conditions. This allows each SCA to operate at optimal high frequencies while the system maintains synchronization across all areas through parameter coordination.
3Manufacturing precision
If distributed PLL arrays are used to actively compensate skew, then clock skew can be minimized, but stability issues arise due to multiple PLLs locking to common reference
Solution Approach 1:
Instead of using multiple PLLs that must lock to a common reference, the system segments the chip into independent SCAs, each with its own TAF-DPS source. This eliminates the stability issues of distributed PLLs while maintaining skew compensation through local synthesis.
Solution Approach 2:
The TAF-DPS acts as an intermediary that synthesizes clock signals with built-in skew compensation capability, replacing the need for complex distributed PLL control systems and their associated stability problems.
4Productivity
If large chip sizes are used to accommodate more transistors, then chip complexity and functionality increase, but clock distribution requires more silicon and metal resources
Solution Approach 1:
The chip is divided into multiple SCAs that can be independently configured and manufactured. Each SCA contains its own TAF-DPS source, eliminating the need for extensive global clock distribution networks and reducing silicon and metal resource requirements.
Solution Approach 2:
Each SCA is designed with local clock generation capability, allowing the system to scale to large chip sizes without proportionally increasing clock distribution resources. Each local area maintains optimal clock signal quality without requiring extensive global routing.
Data Source
AI summary
Circuits for distributing a global clock signal to all clock sinks on a chip for synchronous operation comprises 1) a plurality of synchronous clock areas (SCA), each SCA having a Time-Average-Frequency Direct Period Synthesis (TAF-DPS) clock source for generating a function clock, said TAF-DPS clock source has frequency synthesis and phase adjustment capabilities on its output of function clock; 2) a network for distributing a low frequency global clock signal to said plurality of synchronous clock areas, said global clock signal is used as reference for said TAF-DPS clock sources in all SCAs; 3) a plurality of clock sinks in each SCA, said clock sinks are driven by said function clock generated from said TAF-DPS clock source. Methods of distributing a low frequency global clock signal to all clock sinks in a chip for synchronous operation are also disclosed.