Tag Array Error Detection via Precomputed Parity

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Solution Overview

Problem

Tag arrays in cache systems are vulnerable to data errors due to increasing soft error rates with shrinking feature sizes, leading to performance degradation and logic complexity issues in error handling, particularly in systems without a recovery unit.

Innovation Solution

An effective address directory device with logic for determining expected tags and error detection codes is used to compare with actual tags and codes from the tag array, enabling efficient error detection and prevention of synonyms, and includes a multiplexer for direct mismatch indication, reducing logic delay and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If parity checking is implemented in the critical path for error detection, then data integrity is improved, but logic delay increases which slows down the entire system performance

Engineering Contradiction:
Improvedata integrityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent pre-computes the parity bit for the expected tag before the tag array lookup operation. This preliminary action allows the actual tag retrieval and comparison to proceed without waiting for parity computation during the critical path, thereby maintaining data integrity while avoiding additional logic delay in the critical path.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the error detection process into two independent parts: (1) pre-computation of parity bit for the expected tag, and (2) comparison of stored tag with expected tag after retrieval. This segmentation allows the critical path to focus only on the fastest operation (tag retrieval and comparison) while parity checking occurs in parallel or beforehand, resolving the contradiction between reliability and speed.

Inventive Principle:
Principle #1Segmentation

2Reliability

If additional logic is inserted to enforce one-hot encoding in the critical path, then synonym prevention is improved, but device complexity and logic delay increase

Engineering Contradiction:
Improvesynonym preventionVSAvoidlogic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses feedback from the tag comparison result to control the multiplexer selection. By comparing the stored tag with the expected tag and using the parity bit, the system determines whether a valid match occurred and steers the multiplexer accordingly. This feedback mechanism prevents synonyms without requiring additional one-hot encoding logic in the critical path, reducing complexity while maintaining reliability.

Inventive Principle:
Principle #23Feedback

3Reliability

If recovery unit is added to handle parity errors, then error recovery capability is improved, but device complexity and overhead increase

Engineering Contradiction:
Improveerror recovery capabilityVSAvoidsystem overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service error detection where the tag array itself, through the inclusion of parity bits and the comparison logic, is able to detect and indicate errors without requiring an external recovery unit. The system uses the stored tag and its parity bit to automatically determine if an error occurred during the lookup operation, eliminating the need for additional recovery hardware while maintaining reliability.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7752505B2Method and apparatus for detection of data errors in tag arrays
Publication Date: 2010.07.06 X CORP
  • US7752505B2 patent drawing
  • US7752505B2 patent drawing
  • US7752505B2 patent drawing

AI summary

A method for detecting errors in a tag array includes accessing the tag array with an index, retrieving at least one tag from the tag array, and computing a parity bit based on the expected tag.