Tag Array Two-Step Comparison for Read Disturbance Reduction
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Solution Overview
Problem
Spin-transfer torque magnetic RAM (STT-MRAM) caches face significant read disturbance errors due to stochastic switching behavior during read operations, which existing error correction codes and reduction methods have limited capability to address, especially in tag arrays, leading to high energy consumption and performance penalties.
Innovation Solution
A circuit architecture that reduces read disturbance errors in tag arrays by employing a two-step comparison process using m-bit and n-bit comparators to eliminate unnecessary reads, where lower order bits are compared first to discard mismatched tag ways, thereby reducing the number of read operations and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read current is applied to cache cells during read operation, then read operation can be performed, but contents of cells may flip unintentionally due to stochastic switching behavior
Solution Approach 1:
The tag array is segmented into multiple tag ways, and the comparison process is segmented into two steps: first comparing lower order bits, then comparing higher order bits only for matching tag ways. This segmentation reduces the total number of read operations required.
Solution Approach 2:
The lower order bits of all tag ways are compared first as a preliminary step before comparing higher order bits. This preliminary comparison eliminates mismatched tag ways early, preventing unnecessary read operations on those cells and reducing read disturbance errors.
2Reliability
If error detecting and correcting codes are employed to protect against read disturbance error, then reliability is improved, but energy consumption and area increase
Solution Approach 1:
The patent converts the harmful effect of read disturbance errors into a benefit by using the comparison process itself to identify and eliminate mismatched tag ways early, thereby reducing the total number of read operations and indirectly reducing errors without requiring additional error correction hardware.
3Reliability
If overwriting STT-MRAM cells after each read operation is performed, then read disturbance errors are corrected, but energy consumption increases significantly
Solution Approach 1:
The patent extracts and compares only the necessary bits (lower order bits first, then higher order bits for matching ways) from the tag array, eliminating unnecessary read operations on mismatched tag ways and reducing the frequency of write operations needed to correct read disturbance errors.
4Reliability
If read current is reduced to moderate adverse effects on false read errors, then read disturbance rate decreases, but read latency increases
Solution Approach 1:
The patent performs a partial comparison in two steps: first comparing lower order bits of all tag ways, then comparing higher order bits only for matching tag ways. This partial action approach reduces the total number of read operations while maintaining adequate comparison accuracy to identify cache hits.
Data Source
AI summary
A circuit for reducing read disturbance error in a tag array. The circuit includes a decoder, a plurality of m-bit comparators, and a plurality of n-bit comparators. The decoder is configured to enable access to a respective set of the tag array based on a value of an index of a requested address. Each respective m-bit comparator is configured to enable access to a respective plurality of Most Significant Bits (MSBs) of the respective set responsive to each respective Least Significant Bit (LSB) of a respective plurality of LSBs of the respective set being equal to a respective LSB of a tag of the requested address. Each respective n-bit comparator is configured to enable access to the respective set by a data bus responsive to each respective MSB of the respective plurality of MSBs being equal to a respective MSB of the tag.