Tag Check Skip Logic for Memory Access Latency
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Solution Overview
Problem
Memory-related errors in compiled code, particularly in memory-unsafe languages like C and C++, can lead to unpredictable behavior and security vulnerabilities due to the lack of runtime error checks, making it desirable to provide architectural support for detecting such errors within the instruction set architecture.
Innovation Solution
The implementation of memory access circuitry with tag checking mechanisms that perform checks on guard tags associated with memory blocks, allowing for error reporting and potentially skipping unnecessary tag checks under specific conditions to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tag checking is performed for every memory access operation to detect memory errors, then security and reliability are improved, but processing time and performance deteriorate
Solution Approach 1:
The patent applies partial action by performing tag checks selectively rather than for every memory access. The tag check skip logic determines when a tag check can be omitted based on specific conditions (pending tag checks with matching address tags and overlapping memory blocks), allowing the system to achieve adequate error detection without the overhead of universal checking, thus improving performance while maintaining reliability.
2Measurement precision
If tag checks are performed for all memory operations to ensure memory safety, then detection precision is improved, but processing time increases due to redundant checks
Solution Approach 1:
The patent uses preliminary action by checking conditions before performing a tag check. The tag check skip logic evaluates whether a tag check is necessary based on the state of pending tag checks and address tag matching in advance of the actual memory access, allowing redundant checks to be avoided and processing time to be reduced while maintaining detection accuracy when needed.
3Reliability
If multiple tag checks are performed for overlapping memory operations, then reliability is improved, but device complexity increases due to skip logic
Solution Approach 1:
The patent applies self-service by having the tag check skip logic automatically manage the coordination of multiple tag checks. The logic monitors pending tag checks, compares address tags, determines overlap conditions, and autonomously decides whether to skip a tag check without requiring external control, thereby managing complexity internally while maintaining reliability.
Data Source
AI summary
A tag check performed for a memory access operation comprises determining whether an address tag associated with a target address of the access corresponds to a guard tag stored in the memory system associated with a memory system location to be accessed. A given tag check architecturally required for a tag-checked load operation can be skipped when a number of tag-check-skip conditions are satisfied, including at least: that there is an older tag-checked store operation awaiting a pending tag check, for which a guard tag checked in the pending tag check is associated with a same block of one or more memory system locations as a guard tag to be checked in the given tag check; and that the address tag for the tag-checked load operation is the same as the address tag for the older tag-checked store operation.