Tag-Guarded Memory Access Control via Page Table Mappings
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Solution Overview
Problem
Memory-related errors in compiled code, particularly in memory-unsafe languages like C and C++, are prevalent and vulnerable to exploitation, as they lack runtime error detection, leading to unpredictable behavior and potential security breaches.
Innovation Solution
Implementing tag-guarded memory access mechanisms within the instruction set architecture, where guard tags are associated with memory blocks, and memory access circuitry compares these tags with address tags to control and report errors, with the option to enable or disable guard tag checking based on tag-guard control information in page table mappings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If guard tag checking is performed for all memory accesses, then memory error detection capability is improved, but processing overhead and performance are worsened
Solution Approach 1:
The patent applies local quality by making guard tag checking optional rather than universal. Different memory accesses can have different checking behaviors based on specific conditions, allowing critical memory regions to be checked while non-critical regions skip checking, thus improving reliability where needed without uniformly degrading performance
Solution Approach 2:
The patent implements dynamic control of guard tag checking through condition flags and status registers. The checking behavior can be changed at runtime based on system state, allowing the processor to enable checking when security is prioritized and disable it when performance is critical, resolving the contradiction between reliability and productivity
2Reliability
If guard tag checking is enabled for memory safety, then detection of memory errors is improved, but device complexity is worsened
Solution Approach 1:
The patent achieves universality by integrating guard tag checking functionality into existing memory management structures like page tables and translation lookaside buffers (TLBs). The same hardware components that manage virtual memory addresses are also used to store and check guard tags, adding error detection capability without proportionally increasing device complexity
Solution Approach 2:
The patent merges guard tag information with existing memory metadata structures. Instead of adding separate dedicated hardware for tag checking, the guard tags are combined with page table entries and memory management data structures, allowing multiple functions (address translation and error detection) to share the same hardware resources
3Object-affected harmful factors
If comprehensive guard tag checking is implemented, then memory access security is improved, but performance overhead is worsened
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring guard tags in page table entries before memory accesses occur. The guard tags are established in advance during memory allocation and mapping, so that when accesses happen, the checking is simply a comparison operation rather than a complex validation process, reducing the energy overhead of security checking
Data Source
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AI summary
An apparatus comprises address translation circuitry to perform a translation of virtual addresses into physical addresses in dependence on stored page table mappings between the virtual addresses and the physical addresses. The stored page table mappings comprise tag-guard control information. The apparatus comprises memory access circuitry to perform a tag-guarded memory access in response to a target physical address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target physical address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target physical address. The memory access circuitry is arranged to perform a non-tag-guarded memory access to the addressed location in response to the target physical address without performing the guard-tag check in dependence on the tag-guard control information.