Tag-Guarded Memory Access Control via Region Configuration
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Solution Overview
Problem
Memory-related errors in compiled code, particularly in memory-unsafe languages like C and C++, are prevalent and vulnerable to exploitation, as they lack runtime error checks, leading to unpredictable behavior and potential security threats.
Innovation Solution
Implementing tag-guarded memory access operations within the data processing apparatus, where guard tags are stored with memory blocks and compared with address tags during access, allowing for controlled memory access and error detection, with configuration control information managing these operations on a per-memory-region basis to enhance flexibility and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual guard tags are stored with each memory block for runtime error detection, then memory access security is improved, but memory usage and system complexity increase
Solution Approach 1:
The patent combines multiple guard tags into a single consolidated guard tag structure that can protect multiple memory blocks simultaneously. Instead of storing separate guard tags for each memory block, the system uses a unified guard tag that covers a range of memory addresses, thereby reducing memory overhead while maintaining security across multiple blocks.
Solution Approach 2:
The guard tag mechanism is designed to serve multiple memory blocks with a single guard tag instance. The guard tag structure is made universal by incorporating range-based address matching capabilities, allowing one guard tag to protect multiple memory regions rather than requiring dedicated guard tags for each individual block.
2Reliability
If individual guard tags are stored with each memory block, then runtime error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of multiple individual guard tags into a single consolidated guard tag structure. This consolidation reduces the complexity of managing numerous separate guard tags while maintaining the same error detection capability across multiple memory blocks through unified range-based validation.
3Reliability
If guard tags are checked for every memory access, then memory safety is improved, but processing speed decreases
Solution Approach 1:
The patent implements partial validation by checking only the relevant portions of memory addresses against the guard tag range. Instead of performing exhaustive checks on every byte or word, the system validates at a coarser granularity level using range-based comparison, which reduces the overhead per access while maintaining safety for the protected memory regions.
4Adaptability or versatility
If per-memory-region configuration control information is implemented, then flexibility and efficiency of tag-guarded operations are improved, but device complexity increases
Solution Approach 1:
The patent segments the memory space into distinct regions, each with its own configuration control information and guard tag settings. This segmentation allows different memory regions to have customized protection policies while maintaining a systematic approach to configuration management. The segmentation enables scalable complexity handling by organizing configuration data in a structured, region-based manner.
Data Source
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AI summary
An apparatus and method are provided for controlling memory accesses. The apparatus has memory access circuitry for performing a tag-guarded memory access operation in response to a target address, the tag-guarded memory access operation by default comprising: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and generating an indication of whether a match is detected between the guard tag and the address tag. Further, the apparatus has control tag storage for storing, for each of a plurality of memory regions, configuration control information used to control how the tag-guarded memory access operation is performed by the memory access circuitry when the target address is within that memory region. Each memory region corresponds to multiple of the blocks. This provides a very flexible and efficient mechanism for performing tag-guarded memory access operations.