TAG Memory Error Handling via Cache Hit Forcing
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Solution Overview
Problem
High-performance data processing systems face resilience issues due to corruption of data values stored within the TAG memory of coherency control circuitry, which can lead to erroneous operations, especially in safety-critical environments, and the use of error detection and correction codes introduces an overhead in terms of gate count and power consumption.
Innovation Solution
Incorporating error detection circuitry that forces a hit operation within the cache memory upon detecting errors in the TAG memory, allowing for invalidation of affected storage locations and reloading from main memory to prevent erroneous operations, thereby avoiding the need for error correction and maintaining system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction codes are associated with TAG memory address values, then reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the error correction function from the TAG memory system by removing corrupted entries rather than attempting to correct them. The error detection code identifies corrupted TAG entries, and the system responds by invalidating those specific entries and reloading data from main memory, thereby eliminating the need for complex error correction circuitry while maintaining reliability.
Solution Approach 2:
Instead of correcting errors in the TAG memory entries, the patent inverts the approach by detecting errors and then invalidating the corrupted entries. This inversion transforms the problem from error correction to error detection followed by entry invalidation, significantly reducing the complexity requirements.
2Reliability
If error detection and correction codes are associated with TAG memory address values, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent removes the power-intensive error correction computation by extracting only the error detection function. The system detects errors using simple detection codes and responds by invalidating corrupted TAG entries, avoiding the continuous power consumption associated with active error correction mechanisms.
3Reliability
If a hit operation is forced in cache memory upon TAG memory error detection, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent applies partial action by forcing a hit operation only for the specific cache line associated with the corrupted TAG entry, rather than invalidating the entire cache. This targeted approach maintains data integrity for the affected entry while preserving the performance of all other cache operations.
Solution Approach 2:
The system performs preliminary error detection on TAG memory entries before they cause erroneous operations. By detecting errors early and forcing a hit operation to reload fresh data from main memory, the system prevents corrupted data from being used, maintaining reliability while minimizing performance impact through targeted rather than blanket cache invalidation.
Data Source
AI summary
A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14, 16, 18. The snoop control unit 20 incorporates a TAG memory 22. If an error is detected within an entry of the TAG memory 22, then a hit operation is forced to the corresponding storage location one or more of the data caches 12, 14, 16, 18.