Two-Stage Tag Pipeline for Low-Latency Memory Access
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Solution Overview
Problem
Current way-halting techniques in memory access suffer from high energy consumption, area overhead, and latency issues due to parallel operations and long cycle times, particularly in modern system-on-chip designs.
Innovation Solution
Implementing a two-phase tag pipeline approach with a preamble tag memory and one or more prologue tag memories, where preamble bits are used in the first stage for partial hits, and prologue bits are accessed in the second stage to finalize the hit or miss, reducing unnecessary memory accesses and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ways are accessed simultaneously using an incoming address to find a matching address, then the probability of finding the desired tag is improved, but energy consumption increases substantially
Solution Approach 1:
The tag comparison operation is segmented into multiple stages: a first stage that compares a first portion of the tag (preamble bits) and a second stage that compares a second portion of the tag (prologue bits). This segmentation allows the system to perform partial comparisons and potentially halt earlier, reducing the number of full way accesses required and thereby reducing energy consumption while maintaining lookup reliability.
Solution Approach 2:
The patent applies partial action by performing only the necessary portion of the tag comparison. Instead of always comparing all tag bits across all ways simultaneously, the system performs a first stage comparison on preamble bits and only proceeds to the second stage on prologue bits for ways that passed the first stage. This partial action reduces unnecessary energy consumption while ensuring complete tag verification when needed.
2Use of energy by moving object
If way-halting tag pipeline is implemented with multiple stages, then energy consumption is reduced, but latency increases due to sequential operations
Solution Approach 1:
The tag pipeline is segmented into multiple stages (first stage for preamble bits, second stage for prologue bits), which enables energy savings by performing partial comparisons. The patent addresses the latency issue by optimizing the pipeline structure and using pipelining techniques where the first stage operates independently and the second stage follows only for ways that passed the first stage, reducing the critical path length while maintaining the energy benefits of segmented comparison.
3Manufacturing precision
If full tag address lookup is performed in all ways, then complete tag verification is achieved, but power consumption increases
Solution Approach 1:
The patent implements partial action by performing only the necessary portion of the tag comparison. The first stage compares preamble bits across all ways, and only for ways that produce a partial hit does the system proceed to the second stage to compare prologue bits. This partial action reduces unnecessary power consumption while ensuring complete tag verification (accuracy) is achieved when a full comparison is required.
Solution Approach 2:
The first stage comparison of preamble bits serves as a preliminary action that filters out ways that cannot possibly contain the matching tag. By performing this preliminary comparison before the more expensive second stage comparison, the system reduces overall power consumption while maintaining the accuracy of tag verification for ways that pass the preliminary filter.
Data Source
AI summary
A method of memory access includes, in a first stage, accessing a preamble tag memory and performing a comparison between received preamble bits of an address for lookup and preamble bits stored in the preamble tag memory to generate a partial hit; and, in a second stage, for any partial hits on the preamble bits, accessing a prologue tag memory storing prologue bits corresponding to a second set of bits of the tags to which the preamble bits generated the partial hit in the first stage and performing a corresponding comparison between received prologue bits of the address for lookup and the prologue bits stored in the prologue tag memory to finalize a hit.