Tag Unit Set Hashing for CAM Overload in Cache Memory
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Solution Overview
Problem
Conventional cache memory systems experience inefficiencies due to overloading of specific content-addressable memory units during non-sequential memory access patterns, leading to decreased performance and underutilization of other units.
Innovation Solution
A computer-implemented method that parses virtual addresses into specific portions, reduces even-indexed and odd-indexed bits using XOR trees, and combines these with the middle portion to generate a memory module number, effectively distributing memory access across multiple modules to avoid overloading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional set hashing function is used that computes the set for a given virtual address based on an index portion of the virtual address, then sequential memory accesses are distributed across different CAMs, but non-sequential memory accesses with the same index portion repeatedly query the same CAM causing overload and decreased speed
Solution Approach 1:
The patent changes the parameters used in the hashing function from only the index portion to a combination of the index portion and tag portion of the virtual address. This modification transforms how memory accesses are distributed across CAMs, ensuring that even non-sequential accesses with the same index portion are distributed to different CAMs based on their tag values, thereby preventing overload and maintaining both speed and productivity
Solution Approach 2:
The patent segments the virtual address into different components (index portion and tag portion) and uses both segments in the hashing function. By dividing the address space and utilizing multiple segments for CAM selection, the system achieves better distribution of access patterns across available CAM resources, resolving the contradiction between speed and utilization efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the utilization of memory modules by evenly distributing access, preventing overuse and improving overall memory access speed and resource efficiency.
Implementation Method 1
reducing the even-indexed bits to a first bit, reducing the odd-indexed bits to a second bit, and generating a memory module number by combining the first bit and the second bit
Data Source
AI summary
A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upper, middle, and lower portions. The upper portion is further divided into even-indexed bits and odd-indexed bits. The even-indexed bits are reduced to a single bit using a XOR tree, and the odd-indexed are reduced in like fashion. Those single bits are combined with the middle portion of the virtual address to provide a CAM number that identifies a particular CAM. The identified CAM is queried to determine the presence of a tag portion of the virtual address, indicating a cache hit or cache miss.