Multi-Slice Processor TAGE Branch Prediction Alignment
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Solution Overview
Problem
Current computer processors face inefficiencies in operation speed and power consumption, particularly in data centers and mobile devices, due to limitations in branch prediction mechanisms and address handling.
Innovation Solution
A multi-slice processor is implemented with a tagged geometric history length prediction unit and an effective address table aligned with an update table, allowing for efficient branch prediction and address management through a dispatch network that updates prediction units based on branch instruction outcomes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a multi-slice processor implements a TAGE branch prediction unit with aligned effective address table and update table, then branch prediction accuracy is improved, but device complexity increases
Solution Approach 1:
The processor is divided into multiple execution slices (first execution slice, second execution slice, etc.) that can operate independently and concurrently. Each slice has its own branch prediction capabilities, allowing the system to handle multiple instruction streams simultaneously while maintaining high prediction accuracy for each slice through dedicated TAGE structures.
Solution Approach 2:
The patent implements a hierarchical table structure where the effective address table and update table are nested within the TAGE branch prediction unit. The update table is aligned with the effective address table, creating a compact nested structure that improves cache utilization and reduces memory access latency while maintaining prediction accuracy.
2Measurement precision
If the processor updates both effective address table and TAGE update table for every branch instruction, then prediction accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements selective updating of the TAGE update table based on branch outcome. Only when a branch is taken does the processor update the TAGE update table with the new branch target address and metadata. For non-taken branches, the update is skipped, reducing unnecessary memory writes and power consumption while maintaining prediction accuracy for actually taken branches.
Solution Approach 2:
The branch prediction system uses itself to determine when updates are necessary. The TAGE unit monitors branch outcomes and automatically triggers updates only when needed, eliminating the need for external control logic to manage table updates. This self-regulating mechanism optimizes power consumption by performing updates only when they will actually improve prediction accuracy.
3Productivity
If the processor implements multiple execution slices with full branch prediction capability, then processing throughput is improved, but device complexity increases
Solution Approach 1:
The TAGE branch prediction unit is designed as a shared resource that serves multiple execution slices universally. Rather than implementing separate complete prediction units for each slice, the patent creates a multi-functional TAGE structure that can service predictions for different slices through the aligned effective address and update tables, reducing overall complexity while maintaining high throughput.
Solution Approach 2:
The patent introduces a new dimensional organization to the branch prediction structure by aligning the effective address table and update table in a specific memory hierarchy arrangement. This dimensional reorganization allows multiple execution slices to access the same prediction structures efficiently through differentiated indexing, enabling high throughput without replicating entire prediction units for each slice.
Data Source
AI summary
Operation of a multi-slice processor implementing a tagged geometric history length prediction unit and an effective address table aligned with an update table, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving, at an effective address table and at a TAGE update table, information for a branch instruction dispatched to an execution slice, wherein the effective address table and the TAGE update table are in alignment; responsive to the branch instruction being taken, updating the effective address table and the TAGE update table to indicate the branch instruction being taken; and updating, in dependence upon the alignment between the effective address table and the TAGE update table, the TAGE branch prediction unit with update information from both the effective address table and the TAGE update table.