TAGE Branch Predictor Table Split to Cut RAM Area and Latency
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Solution Overview
Problem
Conventional TAGE branch prediction mechanisms in superscalar processors face increased latency due to the use of RAMs that handle 2-read 1-write and simultaneous read/write, leading to area expansion and wiring length increases, which are not adequately addressed by existing techniques.
Innovation Solution
The implementation of a pipeline architecture where the prediction TAGE table RAM is disposed near the instruction fetch mechanism and the updating TAGE table RAM is near the branch instruction completion point, allowing separate reading and writing operations, with priority given to writing during updates to reduce conflicts and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a RAM that handles 2-read 1-write and simultaneous read/write is used in TAGE branch prediction mechanism, then prediction accuracy is improved through increased number of entries, but area and wiring length increase
Solution Approach 1:
The patent divides the single TAGE table into two separate tables: a first TAGE table dedicated to reading for branch prediction, and a second TAGE table dedicated to writing for updating prediction information. This segmentation allows each table to be optimized for its specific function, reducing the need for complex simultaneous read/write capabilities while maintaining the required number of entries for high prediction accuracy.
Solution Approach 2:
The patent introduces a prediction information updating buffer as an intermediary component between the branch instruction processing unit and the second TAGE table. This buffer temporarily stores prediction information before writing to the second TAGE table, decoupling the read and write operations and eliminating the need for complex simultaneous access mechanisms, thereby reducing RAM area requirements.
2Measurement precision
If a RAM that handles 2-read 1-write and simultaneous read/write is used in TAGE branch prediction mechanism, then prediction accuracy is improved through increased number of entries, but wiring length increases
Solution Approach 1:
By segmenting the TAGE table into separate read-dedicated and write-dedicated tables, the patent eliminates the need for complex wiring required to support simultaneous read/write operations and 2-read 1-write functionality. Each simplified table requires less wiring, reducing overall wiring length despite maintaining sufficient entries for high prediction accuracy.
Solution Approach 2:
The prediction information updating buffer acts as an intermediary that simplifies the data flow between the branch instruction processing unit and the second TAGE table. This intermediary reduces the complexity of wiring required for simultaneous operations by sequencing access operations, thereby reducing overall wiring length.
3Loss of time
If reading and writing are performed simultaneously in TAGE branch prediction, then prediction latency is reduced, but device complexity increases
Solution Approach 1:
The patent segments the TAGE table functionality into separate read and write tables, which simplifies the RAM design by eliminating the need for complex simultaneous access control logic. While this segmentation introduces a buffering step, the overall device complexity is reduced because each table can be implemented with simpler, dedicated access mechanisms rather than complex simultaneous access support.
Solution Approach 2:
The prediction information updating buffer serves as an intermediary that manages the timing and sequencing of write operations to the second TAGE table. This buffer absorbs the timing differences between read and write operations, allowing the use of simpler RAM structures without simultaneous access capabilities while maintaining acceptable prediction latency.
4Area of stationary object
If separate reading and writing operations are implemented with priority to writing, then RAM area is reduced, but potential write delays may occur
Solution Approach 1:
The patent implements preliminary action by having the branch instruction processing unit prepare prediction information and place it in the prediction information updating buffer before the actual write operation to the second TAGE table. This advance preparation allows the write operation to proceed efficiently when the buffer is ready, minimizing delays while using simpler, smaller RAM structures.
Data Source
AI summary
A branch instruction processing unit determines whether a branch has been taken in response to a predetermined branch instruction, detects a branch misprediction, and completes the predetermined branch instruction. A prediction TAGE table RAM stores a prediction TAGE table that is used in branch prediction for fetch. An updating TAGE table RAM stores an updating TAGE table in which information that is similar to information of the prediction TAGE table is registered. In a case where writing for updating is not being performed on the updating TAGE table, an updating determination circuit receives notification of completion information relating to a predetermined branch instruction, acquires information relating to the predetermined branch instruction from the updating TAGE table, and determines whether updating will be performed. In a case where it has been determined that updating will be performed, the updating determination circuit updates the prediction TAGE table and the updating TAGE table.