Tagged Cache for Multi-Domain Debug Coherency
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Solution Overview
Problem
In multi-domain debug operations for integrated circuit systems, maintaining data coherency across overlapping data domains is challenging due to independent data changes in different data views, requiring frequent cache flushing and repopulation in traditional debuggers.
Innovation Solution
A tagged cache system that translates virtual addresses to physical addresses using address translation tables, allowing data reuse and notifications of changes across overlapping address spaces, maintaining coherency without the need for extensive cache flushing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a different cache is used for each data view in traditional debuggers, then data changes can be independently managed, but cache coherency becomes difficult to maintain when data domains overlap
Solution Approach 1:
The patent merges multiple data views into a single unified cache structure instead of using separate caches for each data view. This unified cache uses virtual address tags to distinguish between different data views while sharing the same physical cache space, thereby maintaining data coherency across overlapping domains while allowing independent data change management.
Solution Approach 2:
The patent introduces virtual address tags as an intermediary mechanism that mediates between multiple data views and the unified cache. These tags allow the system to identify which data view a particular cache entry belongs to, enabling coherency management without requiring separate caches for each view.
2Reliability
If caches are flushed and repopulated to maintain coherency in traditional debuggers, then data coherency is restored, but debugging efficiency and productivity decrease
Solution Approach 1:
The patent performs preliminary actions by tagging cache entries with virtual address information upfront, rather than waiting for coherency issues to arise and then flushing the cache. This proactive tagging allows the system to maintain coherency information in the cache itself, avoiding the need for time-consuming cache flushes and repopulation operations during debugging.
3Adaptability or versatility
If multiple separate caches are used for different data views, then each view can manage its data independently, but device complexity increases
Solution Approach 1:
The patent combines multiple data view caches into a single unified cache structure, reducing the number of separate cache components needed. The unified cache uses virtual address tags to maintain the logical separation and independent management capabilities of multiple data views while physically consolidating the cache resources, thereby reducing device complexity.
Data Source
AI summary
A tagged cache is disclosed for data coherency in multi-domain debug operations. Access requests to a memory within a target device are received for data views associated with debug operations, and access requests include virtual addresses associated with virtual address spaces and client identifiers associated with requesting data views. Virtual addresses are translated to physical addresses within a tagged cache using address translation tables that associate virtual addresses from the different virtual address spaces with client identifiers and with physical addresses within the cache. Data within the cache is cached using the physical addresses. Further, when data is written to the cache, virtual address tags within the cache are used to identify if other virtual addresses are associated with the physical address for the write access request. If so, client identifiers stored within the address translation tables are used to notify affected data views of changed data.