Tagged Memory Capacity Isolation for Fail-In-Place Error Handling

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Solution Overview

Problem

Existing memory systems with tagged capacity units face inefficiencies and inflexibility when unrecoverable errors occur, leading to wasted capacity and reduced flexibility in resource allocation.

Innovation Solution

Implement a fail-in-place component in CXL memory devices that records error metrics for tagged capacity units, hides unrecoverable error addresses, and reallocates memory resources efficiently, ensuring continued functionality despite errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional memory error handling is used, then unrecoverable errors cause complete capacity loss, but this leads to wasted memory resources and reduced system flexibility

Engineering Contradiction:
Improvememory reliabilityVSAvoidusable memory capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The memory device is segmented into multiple independently addressable memory sections, each associated with a tag. When an unrecoverable error occurs in one section, only that specific section is excluded from allocation while other sections remain fully accessible. This segmentation allows the system to maintain usable capacity by isolating failures to specific segments rather than losing entire memory devices.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the allocation status parameter of affected memory sections from 'available' to 'excluded' when errors are detected. This parameter change enables dynamic adjustment of usable capacity based on error conditions, allowing the memory device to adapt its operational state without complete failure.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If memory capacity is reduced due to errors, then system reliability improves by excluding bad blocks, but this reduces the quantity of usable memory

Engineering Contradiction:
Improvememory reliabilityVSAvoidmemory allocation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory allocation system is made dynamic through the fail-in-place component, which continuously monitors error metrics and adjusts allocation decisions in real-time. The system can dynamically exclude specific memory sections based on error conditions while maintaining allocation of healthy sections, enabling adaptive resource management that optimizes both reliability and productivity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The fail-in-place component implements feedback mechanisms by monitoring error metrics associated with each memory section and using this information to guide allocation decisions. The system receives feedback about error conditions and adjusts its behavior accordingly, excluding only the necessary portions while maintaining overall system productivity.

Inventive Principle:
Principle #23Feedback

3Reliability

If entire memory devices are replaced when errors occur, then reliability is maintained, but this increases loss of time and reduces resource utilization

Engineering Contradiction:
Improvesystem reliabilityVSAvoiddowntime
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The fail-in-place component performs preliminary error detection and isolation actions before complete system failure occurs. By monitoring error metrics and excluding problematic memory sections proactively, the system prevents cascading failures that would require complete device replacement and extended downtime.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The harmful affected memory sections are extracted from the allocation pool while the rest of the memory device continues to operate. This extraction of only the necessary problematic portions allows the system to maintain reliability by removing error sources while avoiding the need to replace entire memory devices, thereby reducing downtime.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250377962A1Fail-in-place memory device associated with tagged capacity
Publication Date: 2025.12.11 MICRON TECHNOLOGY INC
  • US20250377962A1 patent drawing
  • US20250377962A1 patent drawing
  • US20250377962A1 patent drawing

AI summary

A system can include a memory device comprising a plurality of dynamic capacity devices and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations including recording an error metric associated with a first tag, wherein the first tag is associated with a first memory section of the plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store data; determining whether the error metric satisfies a threshold criterion of unrecoverable error; responsive to determining that the error metric satisfies the threshold criterion, excluding the first memory section from available memory sections of the plurality of dynamic capacity devices for future memory allocation; responsive to receiving a request for memory allocation in the memory device, determining whether a capacity size of the available memory sections of the plurality of dynamic capacity devices is not smaller than a capacity size specified in the request; and responsive to determining that the capacity size of the available memory sections of the plurality of dynamic capacity devices is not smaller than the capacity size specified in the request, identifying a second memory section of the plurality of dynamic capacity devices and associating a second tag with the second memory section.