Tagged Main Memory Cache Lines for Compact Execution Traces

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Solution Overview

Problem

Replayable execution traces generated by modern processors quickly grow large in size due to capturing vast amounts of information, leading to increased processor utilization and storage requirements.

Innovation Solution

Implement cache-based trace logging using tags in a higher memory tier to determine if a cache line influx is already captured by an execution trace, reducing redundant recordings by leveraging tags in the higher memory tier to track whether a value can be reconstructed from prior trace logging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cache-based trace logging is performed without using tags in higher memory tier, then complete execution trace data is captured, but trace file size grows very large and processor utilization increases

Engineering Contradiction:
Improvecompleteness of execution traceVSAvoidtrace file size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies preliminary action by pre-allocating tag space in higher memory tier alongside cache lines before trace logging begins. This allows the system to proactively identify and mark redundant cache lines before they would otherwise be logged, preventing unnecessary trace data generation at the source rather than filtering later.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces tags in higher memory tier as an intermediary mechanism between the cache and trace logging system. These tags act as mediators that carry redundancy information, allowing the trace logging logic to determine whether a cache line influx is redundant without examining the actual cache line data, thus reducing trace file size while maintaining completeness.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If all cache influxes are recorded into execution trace, then accurate replay capability is achieved, but storage requirements and processor utilization increase

Engineering Contradiction:
Improveaccuracy of execution replayVSAvoidprocessor utilization
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent extracts redundant information from the trace logging process by using tags in higher memory tier to identify cache lines that have already been captured. Instead of recording all cache influxes, the system extracts only the necessary unique cache line data, eliminating redundant processing and reducing processor utilization while preserving replay accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter being tracked from the full cache line data to a compact tag indicator in higher memory tier. This parameter change allows the system to efficiently determine redundancy status without processing the actual cache line contents, reducing computational overhead while maintaining the ability to accurately replay execution.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If tags in higher memory tier are used to track captured cache lines, then redundant recordings are reduced, but memory structure complexity increases

Engineering Contradiction:
Improvetrace file sizeVSAvoidmemory structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges the tag structure in higher memory tier with the existing cache line structure, combining redundancy tracking functionality with the memory hierarchy. By integrating tags into the higher memory tier that already exists in the system, the patent avoids adding separate dedicated tracking structures, thus reducing overall complexity while still achieving redundancy reduction.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12411774B2Treating main memory as a collection of tagged cache lines for trace logging
Publication Date: 2025.09.09 MICROSOFT TECHNOLOGY LICENSING LLC
  • US12411774B2 patent drawing
  • US12411774B2 patent drawing
  • US12411774B2 patent drawing

AI summary

Treating main memory as a collection of tagged cache lines for trace logging. A computer system allocates a plurality of memory blocks, and a corresponding plurality of tags, within a main memory. Each tag indicates whether data stored in a corresponding memory block has been captured by an execution trace. The computer system synchronizes these tags with tags in a memory cache and manages a traced status of the memory blocks. This can include one or more of (i) setting a tag to indicate a memory block has not been captured based on identifying a direct memory access operation, (ii) setting a tag based on whether a paged-in value of a memory block has been captured, (iii) setting a tag or memory categorization based whether a memory block has been initialized, or (iv) setting a tag or memory categorization based whether a memory block is mapped to a file.