Tagged Memory Cells With Lower VMIN and Split-Voltage Error Tolerance
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Solution Overview
Problem
Conventional learning machines, such as deep convolutional neural networks (DCNNs), face challenges with memory arrays that have manufacturing defects and errors over time, leading to inefficiencies and increased power consumption due to the need for redundant rows and columns to compensate for faulty memory cells.
Innovation Solution
A system that tags memory cells into low-voltage and high-voltage modes based on their error tolerance, using separate power supplies to optimize operational accuracy and reduce power consumption by utilizing low-voltage cells for fault-tolerant data storage and high-voltage cells for less fault-tolerant data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional learning machines use memory arrays with manufacturing defects, then chip fabrication yield decreases, but adding redundant rows and columns increases device complexity and power consumption
Solution Approach 1:
The patent applies local quality by differentiating between good and bad memory cells within the same memory array. Instead of treating all cells uniformly, the system identifies and tags specific cells with higher error rates, then applies error correction coding selectively to those tagged cells. This localized approach allows the system to compensate for manufacturing defects in specific cells without adding redundancy to the entire memory array, thereby improving yield while minimizing increased complexity.
Solution Approach 2:
The patent changes the parameter of error correction application from a uniform blanket approach to a selective, cell-specific approach. By modifying the error correction parameter (applying ECC only to tagged cells rather than all cells), the system improves fabrication yield by utilizing previously defective cells for error-tolerant applications while avoiding the need for extensive redundant structures throughout the entire memory array.
2Reliability
If redundant rows and columns are added to compensate for faulty memory cells, then reliability improves, but power consumption increases
Solution Approach 1:
The patent applies local quality by implementing error correction selectively only for tagged memory cells that exhibit higher error rates, rather than applying error correction uniformly across the entire memory array. This localized error correction approach maintains reliability for problematic cells while avoiding the unnecessary power consumption that would result from applying error correction to all cells, thereby reducing overall power usage while maintaining required reliability levels.
Solution Approach 2:
The patent applies partial error correction action by using error correction coding only for a subset of memory cells (those tagged as having higher error rates) rather than applying it to all cells. This partial application of error correction maintains sufficient reliability for the tagged cells without the excessive power consumption that would result from applying error correction to the entire memory array, achieving an optimal balance between reliability and power efficiency.
3Reliability
If uniform error correction is applied to all memory cells, then reliability improves, but power consumption and device complexity increase unnecessarily
Solution Approach 1:
The patent applies local quality by differentiating between good and bad memory cells and applying error correction selectively. The system tags cells with higher error rates and applies error correction coding only to those tagged cells, rather than uniformly to all cells. This selective approach maintains data storage reliability for problematic cells while avoiding the unnecessary power consumption and device complexity that would result from uniform error correction application across the entire memory array.
Solution Approach 2:
The patent applies partial error correction by implementing error correction coding only for a subset of memory cells that are tagged as having higher error rates, rather than applying it to all cells. This partial application achieves sufficient data storage reliability for the tagged cells without the excessive power consumption and device complexity that would result from applying error correction uniformly to the entire memory array.
Data Source
AI summary
A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.