Tagged Serial Test Data Capture for Real-Time ATE Decisions

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Solution Overview

Problem

Existing semiconductor Automatic Test Equipment (ATE) systems require extensive software post-processing to interpret test results due to bulk data capture, making real-time data interpretation and decision-making during testing inefficient.

Innovation Solution

Implementing Serial Capture Streaming (SCS) with pattern syntax to tag serial bits of interest, allowing metadata and tagged data to be forwarded for real-time decisions, such as thermal control, during the test process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If bulk data capture is used during integrated circuit testing, then all test data is captured, but extensive software post-processing is required making real-time data interpretation inefficient

Engineering Contradiction:
Improvetest data capture completenessVSAvoidsoftware post-processing time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent extracts only the necessary test data bits from the bulk serial data stream using a data selector. Instead of capturing all serial test data and processing it afterward, the system identifies and extracts only the relevant bits during the testing phase, eliminating the need for extensive post-processing software while maintaining complete capture of necessary information.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs data selection and extraction during the testing phase itself rather than afterward. The data selector is configured to identify and capture specific bits of interest in real-time as serial data flows through the system, allowing immediate availability of processed data without requiring subsequent software intervention.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If all serial test data is captured during testing, then complete data is obtained, but real-time data interpretation and decision-making becomes inefficient

Engineering Contradiction:
Improvetest result accuracyVSAvoidreal-time processing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system extracts only the essential test data bits needed for accurate test results while discarding unnecessary data during the testing process. This extraction approach maintains the reliability of test outcomes by capturing all necessary information while dramatically improving real-time processing efficiency by eliminating redundant data handling.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of processing all serial data bits, the patent applies partial action by selecting and processing only the specific portion of data bits that are necessary for test evaluation. The data selector is configured to capture exactly the required amount of information without the excessive processing of unnecessary data, optimizing both accuracy and efficiency.

Inventive Principle:
Principle #16Partial or excessive action

3Manufacturing precision

If extensive data is captured for testing, then comprehensive test coverage is achieved, but processing time increases reducing overall testing efficiency

Engineering Contradiction:
Improvetest coverage completenessVSAvoiddata processing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent extracts precisely the data bits required for comprehensive test coverage from the serial data stream. The data selector identifies and captures only the essential bits needed for complete test evaluation, achieving full manufacturing precision in test coverage while minimizing processing time by eliminating unnecessary data extraction and handling.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250208195A1Method and apparatus to select a portion of serial test data received from an integrated circuit to capture during test of the integrated circuit
Publication Date: 2025.06.26 INTEL CORP
  • US20250208195A1 patent drawing
  • US20250208195A1 patent drawing
  • US20250208195A1 patent drawing

AI summary

A test pattern syntax allows cycles of interest for a device to be tagged as serial protocol data sources during test of the integrated circuit in semiconductor automatic test equipment (ATE). A test pattern syntax is used to tag serial bits of interest. Metadata (from serial capture control contents) in combination with the tagged serial bits of interest received during the test of the integrated circuit is used to identify data in the tagged serial bits of interest. Data in the with tagged serial bits of interest is sent to other location(s) in the automated test equipment. The data in the tagged serial bits of interest can be used for real time decisions (such as thermal control) or plotted in a Graphical user interface (GUI) during test of the integrated circuit.