Tagless Access Buffer Cache Architecture for Processor Energy Efficiency
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Solution Overview
Problem
Existing processor designs face challenges in optimizing both performance and energy efficiency, particularly in battery-powered devices and large-data scientific computing applications, where existing techniques for improving energy efficiency are limited and may increase energy expenditure.
Innovation Solution
The implementation of a Tagless Access Buffer (TAB) system architecture that includes a clock signal generator, CPU, data register file, and memory unit with a hierarchical cache structure, utilizing metadata to optimize memory references and reduce energy consumption by predicting access patterns and allocating memory references to a TAB for efficient data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing energy efficiency techniques (such as multiscore scaling) are used, then energy consumption is reduced, but performance is limited
Solution Approach 1:
The patent segments the cache system into multiple specialized caches (L1 data cache, L1 instruction cache, L2 cache, and filter cache) with distinct functions. The filter cache specifically segments the caching function to handle instruction fetches separately, allowing the main L1/L2 caches to focus on data access. This segmentation enables each cache to be optimized for its specific purpose, improving overall energy efficiency while maintaining performance.
Solution Approach 2:
The filter cache acts as an intermediary component between the processor and the L1/L2 cache hierarchy. It intercepts and handles instruction fetch requests before they reach the main data caches, reducing unnecessary access to larger, more power-consuming cache levels. This intermediary structure resolves the contradiction by routing traffic efficiently based on access type.
2Productivity
If performance-critical techniques are implemented, then processor performance is improved, but energy expenditure increases significantly
Solution Approach 1:
The patent applies local quality by giving different cache structures different characteristics optimized for their specific access patterns. The filter cache uses a direct-mapped structure with small size for fast instruction fetches, while the L1 data cache uses a more complex set-associative structure for data access. This localized optimization allows each component to achieve high performance for its specific function while consuming minimal energy.
Solution Approach 2:
The filter cache performs preliminary action by handling instruction fetch requests in advance, before they can consume more energy in the L1/L2 data caches. By predicting and caching instruction fetch patterns upfront, the system prevents energy-intensive access to larger cache levels while maintaining performance.
3Speed
If a traditional cache hierarchy is used, then data access is handled, but tag comparison overhead increases energy consumption
Solution Approach 1:
The patent extracts the tag comparison function from the traditional cache hierarchy by implementing a tagless filter cache. Instead of performing full tag comparisons in the L1/L2 caches for every access, the filter cache uses a simplified indexing mechanism that eliminates the need for energy-consuming tag comparisons for instruction fetches. This extraction of the tag comparison function resolves the contradiction between fast access and low energy consumption.
Data Source
AI summary
Certain embodiments herein relate to using tagless access buffers (TABs) to optimize energy efficiency in various computing systems. Candidate memory references in an L1 data cache may be identified and stored in the TAB. Various techniques may be implemented for identifying the candidate references and allocating the references into the TAB. Groups of memory references may also be allocate to a single TAB entry or may be allocated to an extra TAB entry (such that two lines in the TAB may be used to store L1 data cache lines), for example, when a strided access pattern spans two consecutive L1 data cache lines. Certain other embodiments are related to data filter cache and multi-issue tagless hit instruction cache (TH-IC) techniques.