Tag-less Cache Victim Buffer for Eviction Latency

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Solution Overview

Problem

Tag-less cache systems lack efficient buffer functionality for evicted cache lines, as they do not have address tags, making it difficult to quickly remove and replace cache lines, which can lead to performance issues and increased latency in multiprocessor systems.

Innovation Solution

Implementing a victim buffer (VB) that stores evicted cache lines with their address tags, allowing for quick disposal and replacement by indexing similarly to L1 and L2 caches, using location information to manage cache line evictions and write-back operations without the need for address comparisons.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If tag-less cache systems are used to simplify cache structure and reduce overhead, then device complexity is reduced, but buffer functionality for evicted cache lines becomes inefficient due to lack of address tags

Engineering Contradiction:
Improvecache structure complexityVSAvoideviction and replacement efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The cache system is segmented into two distinct parts: a tag-less cache for normal operations and a separate victim buffer for handling evicted lines. This segmentation allows each component to have optimized functionality - the cache remains simple while the buffer provides the necessary address tracking capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The victim buffer acts as an intermediary between the tag-less cache and main memory. It temporarily holds evicted cache lines with their address tags, enabling efficient management of cache replacements without requiring the main cache structure to maintain address tags for all lines.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If address tags are stored with every cache line to enable quick identification and replacement, then eviction and replacement efficiency is improved, but device complexity and memory overhead increase

Engineering Contradiction:
Improveeviction and replacement efficiencyVSAvoidcache structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Address tags are not uniformly applied to all cache lines but are selectively stored only for evicted lines in the victim buffer. This local application of address tagging provides the necessary identification capability exactly where needed - during eviction and replacement operations - without adding overhead to the entire cache structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of maintaining address tags for all cache lines (excessive action), the system maintains tags only for the subset of lines that have been evicted and are pending replacement (partial action). This partial tagging approach provides sufficient functionality for efficient replacement while minimizing complexity.

Inventive Principle:
Principle #16Partial or excessive action

3Loss of time

If evicted cache lines are immediately written back to memory without buffering, then loss of time for buffer management is reduced, but latency increases due to direct memory access requirements

Engineering Contradiction:
Improvebuffer management timeVSAvoidcache line eviction latency
Core Design Contradiction:
Loss of timeVSDuration of action of moving object

Solution Approach 1:

The victim buffer performs preliminary action by temporarily holding evicted cache lines with their address information before the actual write-back to memory occurs. This preliminary buffering allows the system to prepare replacement lines in advance and manage evictions more efficiently without immediately accessing slow memory.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The victim buffer serves as an intermediary structure between the cache and main memory, decoupling the eviction decision from the actual write-back operation. This intermediary allows the cache to proceed with replacement operations while the buffer handles the slower memory write-back in the background.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3486787B1Systems and methods for tag-less buffer implementation
Publication Date: 2022.09.28 SAMSUNG ELECTRONICS CO LTD
  • EP3486787B1 patent drawingFigure 1
  • EP3486787B1 patent drawingFigure 2
  • EP3486787B1 patent drawingFigure 3

AI summary

A data management method for a computer system including at least one processor (710) and at least a first cache (720), a second cache (740), a victim buffer (771), and a memory (780) allocated to the at least one processor (710), includes selecting a victim cache line to be evicted from the first cache; finding a victim buffer location corresponding to the victim cache line from a set of the victim buffer; copying data of the victim cache line to a data field of the victim buffer location; copying a backward pointer (BP) associated with the victim cache line to a backward pointer field of the victim buffer location; and reclaiming victim space of the first cache (720) using the victim buffer (771).