Tail-Bit Controller Calibrates Program Voltage for NAND Flash Memory
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Solution Overview
Problem
NAND flash memory devices face issues with process variations leading to tail-bit memory cells being over-programmed, causing read errors due to differences in programming speeds among memory cells, resulting in inefficient programming operations and potential errors.
Innovation Solution
A nonvolatile memory device with a tail-bit controller that calibrates distinct program start voltages for normal and tail-bit memory cells based on tail-bit flag information, allowing for separate programming of pages with and without tail-bit cells, thereby reducing operational errors and programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the same program voltage is applied to all memory cell transistors, then the programming operation is simple and fast, but tail-bit memory cell transistors are over-programmed causing read errors
Solution Approach 1:
The patent segments the memory cell transistors into two groups: normal memory cell transistors and tail-bit memory cell transistors. Different program voltages are applied to each group based on their programming characteristics. This segmentation allows normal cells to be programmed efficiently while preventing over-programming of tail-bit cells, thus resolving the contradiction between programming speed and read accuracy.
Solution Approach 2:
The patent applies different program voltages to different locations/groups of memory cell transistors based on their local characteristics. Tail-bit memory cell transistors receive a different program voltage compared to normal memory cell transistors. This local quality adjustment ensures that each group receives the appropriate voltage for its specific programming speed, maintaining both high productivity and reliability.
2Reliability
If a lower program voltage is used to prevent over-programming of tail-bit cells, then read errors are reduced, but programming time increases due to slower programming of normal cells
Solution Approach 1:
By segmenting memory cell transistors into normal and tail-bit groups, the patent can apply optimized program voltages to each segment simultaneously. Normal cells receive higher voltage for fast programming while tail-bit cells receive lower voltage to prevent over-programming. This eliminates the need to use a conservative voltage for all cells, thus reducing total programming time while maintaining read accuracy.
Solution Approach 2:
The patent changes the program voltage parameter based on the type of memory cell transistor being programmed. Different voltage levels are assigned to different cell types, allowing each to be programmed at its optimal speed without causing over-programming. This parameter differentiation resolves the time-loss issue while maintaining reliability.
3Manufacturing precision
If process variations are reduced to achieve uniform memory cell characteristics, then tail-bit issues are eliminated, but manufacturing complexity and cost increase
Solution Approach 1:
The patent implements a feedback mechanism where memory cell transistors are classified into normal and tail-bit groups based on their programming characteristics. This feedback allows the system to adapt to process variations by identifying and differently treating tail-bit cells. Instead of requiring extremely tight process control to eliminate all variations, the system responds to variations by applying different program voltages, thus reducing manufacturing complexity while maintaining uniformity.
Solution Approach 2:
Rather than focusing solely on reducing process variations through complex manufacturing control, the patent changes the operating parameter (program voltage) based on the observed characteristics of memory cell transistors. This approach accepts normal process variations but compensates for them through parameter adjustment, reducing manufacturing complexity while achieving uniform programming results.
Data Source
AI summary
A nonvolatile memory device may include a memory cell array adapted to store tail-bit flag information indicating tail-bit memory cells, and a tail-bit controller adapted to calibrate a program start voltage of normal memory cells and a program start voltage of the tail-bit memory cells independently based upon the tail-bit flag information.