Tail-Biting Data Decoding Circuit for Low-Power IoT Reception
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Solution Overview
Problem
In low power wide area networks, especially for IoT applications, devices face high packet error rates, leading to increased power dissipation and reduced battery life due to frequent signal retransmissions during data reception.
Innovation Solution
A decoding circuit and method utilizing tail-biting convolutional code technology and the Viterbi algorithm to identify and concatenate unknown and known bit sections, reducing the search order and power dissipation by maintaining decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional decoding methods are used, then decoding performance is maintained, but power dissipation increases and battery life decreases due to frequent signal retransmissions
Solution Approach 1:
The encoded data is segmented into three distinct sections: first unknown bit section, known bit section, and second unknown bit section. This segmentation allows the Viterbi algorithm to process only the unknown sections while utilizing the known section as reference information, reducing the decoding search space and power consumption while maintaining reliable decoding performance.
Solution Approach 2:
The known bit section is identified and prepared in advance before the main decoding process. This preliminary identification of known bits allows the decoder to use this information as a reference during Viterbi algorithm execution, reducing the need for retransmissions and thereby decreasing power dissipation while maintaining packet error rate performance.
2Reliability
If signal retransmissions are increased to improve packet error rate, then decoding accuracy increases, but power dissipation increases and battery life decreases
Solution Approach 1:
By segmenting the data into unknown and known bit sections, the invention enables more accurate first-time decoding, reducing the need for retransmissions and thereby extending battery life while maintaining or improving packet error rate performance.
Solution Approach 2:
The known bit section serves as feedback information that guides the Viterbi algorithm during decoding. This feedback mechanism improves decoding accuracy on the first attempt, reducing retransmissions and extending battery life while maintaining reliable packet error rate performance.
3Reliability
If data is concatenated and decoded using Viterbi algorithm with known bit information, then packet error rate decreases, but device complexity increases
Solution Approach 1:
The decoding circuit is designed with segmented processing stages: identification of known bit sections, selective concatenation of unknown bit sections, and targeted Viterbi algorithm application. This segmented approach reduces unnecessary processing complexity while maintaining improved packet error rate performance through intelligent use of known bit information.
Data Source
AI summary
The present invention discloses a data decoding circuit. A data reforming circuit receives encoded data encoded by using tail-biting convolutional code to identify a first unknown bit section, a known bit section and a second unknown bit section in an order to further connect the second unknown bit section and the first unknown bit section in series to generate data to be decoded. A decoding circuit decodes the data to be decoded by using Viterbi algorithm and at least one piece of known bit information to generate a decoded result that includes a second decoded bit section and a first decoded bit section respectively corresponding to the second unknown bit section and the first unknown bit section. A data restoring circuit connects the first decoded bit section, a known decoded bit section corresponding to the known bit section and the second decoded bit section in series to generate decoded data.