Input Buffer Tail-Node Control for Fast Low-Power Memory I/O
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high data reliability, fast memory access speeds, and reduced power consumption while accommodating a wide range of input signals, particularly in low-power double data rate synchronous DRAM applications like LPDDR4, where existing input receiver circuits struggle to efficiently process address, command, and clock signals.
Innovation Solution
The implementation of a data latch type input buffer with differential amplifiers that amplify data signals and latch them based on a voltage difference between the data input signal and a reference voltage, using a clock signal to perform amplification and precharge operations during each clock cycle, while also incorporating a voltage control circuit to manage power supply noise and optimize signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the input receiver circuit operates at higher speed to increase memory access speed, then access speed is improved, but power consumption increases
Solution Approach 1:
The input receiver circuit dynamically adjusts its operating characteristics based on signal conditions. The differential amplifier and latch circuitry operate in different modes depending on whether precharging or amplification is needed, allowing the circuit to optimize between speed and power consumption for different operational phases
Solution Approach 2:
The circuit performs periodic precharging operations during clock low periods and amplification operations during clock high periods. This periodic alternation between preparation (low power) and active processing (high speed) modes enables the circuit to achieve high average access speed while maintaining lower average power consumption
2Adaptability or versatility
If the input receiver circuit is designed to accommodate a wide range of input signals, then adaptability is improved, but device complexity increases
Solution Approach 1:
The differential amplifier circuit serves multiple functions: it acts as a precharger during clock low periods and as an amplifier during clock high periods. This multi-functionality allows a single circuit structure to handle various signal conditions and voltage levels, accommodating a wide range of input signals without requiring separate dedicated circuits for each function
Solution Approach 2:
The circuit accommodates different input signal characteristics by changing its operational parameters based on the clock signal phase and input voltage levels. The differential amplifier adjusts its gain and operating point dynamically, enabling it to process signals across a wide voltage range (10%-42% of VDD) while maintaining a relatively simple circuit structure
3Reliability
If the differential amplifier amplifies the voltage difference between data input signal and VREF, then data reliability is improved, but sensitivity to power supply noise increases
Solution Approach 1:
The reference voltage VREF serves as an intermediary that provides a stable comparison point for the differential amplifier. By amplifying the difference between the data signal and this stable reference rather than amplifying the raw data signal directly, the circuit achieves high reliability while the reference voltage acts as a buffer against power supply noise variations
Solution Approach 2:
The circuit extracts and amplifies only the differential voltage component between the data signal and reference voltage, separating the useful signal information from the common-mode noise. This differential extraction method inherently rejects power supply noise that appears equally on both inputs, improving reliability while reducing noise sensitivity
Data Source
AI summary
Apparatuses for receiving an input data signal are described. An example apparatus includes: a plurality of data input circuits and an internal data strobe generator. Each data input circuit of the plurality of data input circuits includes: an amplifier that receives data from a data terminal, and latches the data in an enable state and refrains from latching data in a disable state; and a voltage control circuit coupled to a tail node of the amplifier and provides a first voltage to the tail node during the enable state, and further provides a second voltage different from the first voltage to the tail node in a first mode and to sets the tail node in a floating state in a second mode during the disable state. The internal data strobe signal generator provides a plurality of internal data strobe signals to the plurality of corresponding data input circuits respectively.