Tailbiting Viterbi Decoding With Subblock Concatenation
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Solution Overview
Problem
The complexity of Viterbi decoders in wireless networks increases with the number of states in convolutional codes, leading to inefficiencies in decoding tailbiting codes, especially in standards like IEEE 802.11a, 802.11b, 802.11g, 802.11n, 802.16, and 802.20, due to unknown starting and ending states, which complicates decoding and requires additional memory and processing power.
Innovation Solution
A low complexity tailbiting Viterbi decoder method that involves concatenating sequences to the serial data block, estimating starting and ending states, and outputting an internal portion of the decoded block, either by appending and prepending subblocks, sequentially decoding, or appending/prepending initial/terminal subblocks to simplify the decoding process without adding overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of states in convolutional codes is increased to improve error correction performance, then the reliability of data transmission is improved, but the decoding complexity of Viterbi decoders increases significantly
Solution Approach 1:
The patent segments the decoding process into multiple passes, where each pass processes a portion of the trellis structure. Instead of computing all possible paths simultaneously through the entire trellis, the decoder divides the computation into manageable segments corresponding to different state transitions, reducing the memory and computational requirements at any given time.
Solution Approach 2:
The patent performs preliminary computations to identify and store only the most promising paths through the trellis structure before final decoding. By pre-calculating and retaining only the survivor paths at each stage, the system reduces the complexity of subsequent decoding operations while maintaining decoding accuracy.
2Loss of information
If tailbiting convolutional codes are used to eliminate overhead bits and improve spectral efficiency, then the loss of information is reduced, but the decoding complexity increases due to unknown starting and ending states
Solution Approach 1:
The patent implements a feedback mechanism where the decoder iteratively refines its estimates of the starting and ending states. By using the decoded output to update and re-evaluate the state estimates in subsequent decoding passes, the system converges to the correct tailbiting states without requiring explicit overhead bits to define them.
Solution Approach 2:
The patent employs dynamic programming techniques adapted for tailbiting codes, where the decoding process dynamically adjusts state probabilities based on received signals and previous decoding results. This allows the decoder to handle the cyclic nature of tailbiting codes efficiently by continuously updating state estimates rather than using fixed state assumptions.
3Measurement precision
If conventional Viterbi decoding is used for tailbiting codes with unknown states, then the measurement precision of state estimation is improved, but the device complexity and memory requirements increase
Solution Approach 1:
The patent applies local quality by focusing computational resources on estimating the state at specific critical points in the trellis (such as the middle point or endpoints) rather than maintaining precise state information throughout the entire trellis structure. This selective state estimation reduces memory requirements while maintaining sufficient accuracy for reliable decoding.
Solution Approach 2:
The patent extracts and processes only the essential state information needed for tailbiting decoding, separating the critical state estimation problem from the full trellis processing. By extracting only the necessary state variables and processing them independently, the system reduces memory requirements while preserving state estimation accuracy.
Data Source
AI summary
Methods, software, circuits and systems involving a low complexity, tailbiting decoder. In various embodiments, the method relates to concatenating an initial and/or terminal subblock of the serial data block and outputting decoded data from an internal block of the modified data block. The circuitry generally includes a buffer, logic configured to concatenate an initial and/or terminal subblock to the serial data block, and a decoder configured to decode the data block, estimate starting and ending states for the data block, and output an internal portion of the serial data block and the one or more sequences as decoded data. The invention advantageously reduces the complexity of a suboptimal convolutional decoder, ensures smooth transitions at the beginning and end of the serial data block during decoding, and increases the reliability of the starting and ending states, without adding overhead to the transmitted data block.