Tailless Current-Steering DAC with Feedback-Controlled Common Mode
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Solution Overview
Problem
Traditional tailless high-speed digital-to-analog converters (DACs) suffer from linearity issues due to the output common mode being constrained by Vout_CM=(VDD-12*Idac*RL), which creates margin problems for NMOS transistors, especially in high-swing applications.
Innovation Solution
A high-linearity tailless current-steering digital-to-analog converter employing linearization techniques, including a common-mode feedback controlled PMOS parallel tailless DAC, adjustable reference voltage generation, and controllable output swing through a programmable current source, to overcome linearity constraints and improve transistor reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional tailless high-speed DAC structure is used with fixed output common mode constraint, then high-speed performance is achieved, but linearity deteriorates and NMOS transistor margin problems occur in high-swing applications
Solution Approach 1:
The patent implements dynamic control of the output common mode voltage through a feedback mechanism. The common mode voltage is no longer fixed but is dynamically adjusted based on the differential input signals and feedback from the output, allowing the system to maintain optimal operating conditions while achieving high linearity in high-swing applications
Solution Approach 2:
A feedback circuit is introduced that monitors the output common mode voltage and adjusts the bias conditions accordingly. The feedback mechanism uses the differential input signals to control the common mode level, creating a self-regulating system that maintains linearity across the full swing range without compromising high-speed performance
2Adaptability or versatility
If higher swing is achieved to meet application requirements, then output range is improved, but output common mode decreases creating margin problems for NMOS transistors
Solution Approach 1:
The feedback circuit dynamically adjusts the common mode voltage based on the instantaneous signal conditions. When the output swing increases, the feedback mechanism automatically raises the common mode level to maintain adequate NMOS transistor margins, thereby preserving reliability across the full output range
Solution Approach 2:
The patent changes the operating parameters of the NMOS transistors dynamically by adjusting the common mode voltage. This parameter adjustment ensures that the transistors operate in the optimal region regardless of the signal swing amplitude, maintaining both high swing capability and sufficient design margins
Data Source
AI summary
Disclosed in the present application is a high-linearity tailless current steering digital-to-analog converter (DAC). The high-linearity tailless current steering DAC comprises: several bit digital-to-analog conversion units, an operational amplifier and a current source. Each unit comprises: first and second load PMOS transistors, first and second load resistors, and first to fourth NMOS transistors, wherein a drain terminal of the first load PMOS transistor is connected to a drain terminal of the first NMOS transistor and an end of the first load resistor, a drain terminal of the second load PMOS transistor is connected to a drain terminal of the second NMOS transistor and an end of the second load resistor, a source terminal of the first NMOS transistor is connected to a drain terminal of the third NMOS transistor, a source terminal of the second NMOS transistor is connected to a drain terminal of the fourth NMOS transistor, and gate terminals of the third and fourth NMOS transistors are respectively connected to a pair of differential input signals. Gate terminals of the first and second load PMOS transistors are connected to an output of the operational amplifier, the other ends of the first and second load resistors are connected to a positive input terminal of the operational amplifier, and a negative input terminal of the operational amplifier is connected to a reference voltage. The current source is connected to gate terminals of the first and second NMOS transistors. Accordingly, a high-linearity tailless DAC is implemented in high-speed and high-swing applications.