Tall Power Lines With Aligned Signal Wires for Lower Resistance
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Solution Overview
Problem
As lithographic feature size decreases, the cross-sectional area of power-carrying lines in integrated chips decreases, leading to increased resistance and power dissipation as waste heat, which reduces efficiency and can damage the device.
Innovation Solution
Increasing the height of power-carrying lines while maintaining the areal density, thereby decreasing line resistance without sacrificing the number of lines that can be fit on the chip, and using a dielectric cap and vias to manage signal lines and prevent unintended shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the cross-sectional area of power-carrying lines is decreased to maintain areal density, then the number of lines that can be fit on the chip is improved, but the line resistance increases
Solution Approach 1:
The patent transitions from two-dimensional planar power lines to three-dimensional vertically-aligned power lines. By extending power lines in the vertical dimension (through multiple layers and via connections), the patent increases the effective cross-sectional area for power transport without increasing the lateral footprint, thereby maintaining areal density while reducing resistance.
Solution Approach 2:
The patent implements nested power line structures where vertical power lines are positioned within or adjacent to signal line layers. The dielectric cap embeds vertical power line segments within the horizontal signal line layer, creating a nested configuration that maximizes space utilization and reduces resistance through increased vertical conductivity paths.
2Reliability
If the height of power-carrying lines is increased to decrease resistance, then the electrical characteristics are improved, but the alignment with signal lines becomes more difficult
Solution Approach 1:
The patent segments power lines into vertical segments connected by horizontal segments. The dielectric cap creates discrete vertical power line segments within the signal line layer, with horizontal connections at different heights. This segmentation allows each segment to be optimized independently for both electrical performance and alignment precision.
Solution Approach 2:
The dielectric cap acts as an intermediary structure that facilitates precise alignment between vertical and horizontal power line segments. By providing a defined embedding structure within the signal line layer, the dielectric cap enables accurate positioning of vertical power lines without requiring direct alignment between disparate layers.
Data Source
AI summary
Devices and methods of forming the same include a first conductive line having a top surface at a first height above an underlying layer. A second conductive line, parallel to the first conductive line, has a second height above the underlying layer that is greater than the first height. A first interlayer dielectric layer, between the first conductive line and the second conductive line, has a top surface at a third height above the underlying layer that is greater than the first height and that is less than the second height.