On-Chip Tamper Detection With CeRAM Kill Switch Memory
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Solution Overview
Problem
Conventional computer systems lack effective mechanisms to detect and respond to unauthorized access and tampering attempts, particularly in the presence of sophisticated cyberattacks that target on-chip components, which can lead to compromised security and functionality.
Innovation Solution
The implementation of a tamper detection and response system utilizing correlated electron random access memory (CeRAM) that includes a kill switch mechanism, attack signature storage, and notification protocols to inhibit or prevent attacks by disabling chip functionality and informing maintainers of potential intrusions, with tight integration of non-volatile memory with logic to ensure persistent security measures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional computer systems are used without specialized tamper detection mechanisms, then device complexity is reduced and ease of operation is maintained, but security reliability deteriorates due to inability to detect and respond to sophisticated cyberattacks
Solution Approach 1:
The patent embeds tamper detection circuitry, performance monitors, and kill switch logic directly within the processor chip structure. The detection mechanisms are nested inside the same physical substrate as the logic circuitry being protected, allowing intimate integration without adding external complexity. This nesting approach enables security functions to coexist with computational functions in a unified device architecture.
Solution Approach 2:
The patent combines multiple security functions into unified circuit blocks: performance monitors that track both computational metrics and tamper indicators, kill switch logic that integrates with normal control logic, and non-volatile memory that stores both operational data and security signatures. This merging reduces overall device complexity by eliminating separate security hardware modules.
2Reliability
If non-volatile memory is tightly integrated with logic circuitry for persistent security measures, then security reliability is improved through persistent kill switch functionality, but device complexity increases due to tight integration requirements
Solution Approach 1:
The non-volatile memory cells are physically nested within or adjacent to the logic circuitry blocks they protect. The kill switch bits are stored in non-volatile memory that is tightly coupled to the computational units, enabling persistent security state without requiring separate security memory modules. This spatial nesting achieves tight integration while maintaining functional independence.
Solution Approach 2:
The non-volatile memory serves dual purposes: storing security-related kill switch states and preserving computational data across power cycles. This multi-functionality reduces the need for dedicated security memory, thereby reducing overall device complexity while maintaining persistent security capabilities.
3Measurement precision
If attack signatures are stored in non-volatile memory for pattern matching, then measurement precision of tamper detection is improved, but device complexity increases due to storage and comparison mechanisms
Solution Approach 1:
The performance monitors track a selective subset of computational events that are most indicative of tamper attempts, rather than monitoring all possible operations. The system stores and compares only the most critical attack signatures in non-volatile memory, focusing detection resources on high-probability threats. This partial monitoring approach achieves sufficient detection precision while minimizing the complexity of storage and comparison mechanisms.
Solution Approach 2:
Different regions of the processor chip have specialized detection capabilities tailored to local vulnerability patterns. Attack signatures and detection logic are distributed across the chip architecture, with each logic block having access to relevant security patterns stored in locally-coupled non-volatile memory. This localized approach improves detection precision for specific attack vectors without requiring a centralized complex detection system.
4Reliability
If kill switch mechanisms are implemented to disable chip functionality upon tamper detection, then security reliability is improved by preventing further exploitation, but ease of operation deteriorates due to system shutdown
Solution Approach 1:
The kill switch mechanism is implemented as a dynamic, conditional response rather than a static shutdown. The non-volatile memory bits that control the kill switch can be selectively set or cleared based on the nature and severity of detected tamper events. This dynamic control allows the system to maintain operational availability for legitimate users while enforcing security shutdowns only when actual threats are confirmed, balancing security enforcement with system usability.
Data Source
AI summary
Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).